MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 468

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10-38
Offset Channel 1: 0x3_110C
Reset
Reset
0–28
Bits
W
W
29
30
R
R
Channel 2: 0x3_120C
Channel 3: 0x3_130C
Channel 4: 0x3_140C
Channel 1: 0x3_110C
Channel 2: 0x3_120
Channel 3: 0x3_130C
Channel 4: 0x3_140C
32
0
Name
CON
NPR
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Reserved, should be set to zero.
No-Pop-Reset
0 No special action.
1 Causes the same channel reset actions as the CON bit, except that the fetch FIFO is left
Continue bit
0 No special action.
1 Causes the same channel reset actions as bit R, except that the fetch FIFO and bits
Figure 10-11. Channel Configuration Register (CCR)
• If the NPR bit is set while the channel is requesting an EU assignment from the
• If the NPR bit is set after the channel has been assigned one or more EUs, the channel
• If the CON bit is set while the channel is requesting an EU assignment from the
• If the CON bit is set after the channel has been assigned one or more EUs, the channel
Table 10-11. Channel Configuration Register Fields
unchanged, such that the channel picks up by re-fetching the previous descriptor. This
permits debug of a descriptor in-place without having to rewrite the descriptor pointer
into the fetch FIFO.
controller, the channel cancels its request.
requests a write from the controller to set the software reset bit of each reserved EU. The
channel then releases the EU(s).
32-63 of the CCR register are not cleared. After the reset sequence is complete, this bit
automatically returns to 0 and the channel resumes normal operation, servicing the next
descriptor pointer in the fetch FIFO, if any.
controller, the channel cancels its request.
requests a write from the controller to set the software reset bit of each reserved EU. The
channel then releases the EU(s).
50
PBS
51
1
.
1
.
52
—
54
—
BS
55
All zeros
All zeros
IWSE
56
Description
—
57
EAE CDWE AWSE
58
59
28
60
Freescale Semiconductor
NPR
NT
29
61
Access: Read/Write
CDIE
CON
30
62
31
63
—
R