MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 958

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14-210
Set up the MII Mgmt for a write cycle to the external PHY Auxiliary Control and Status Register to configure the PHY through
Set up the MII Mgmt for a write cycle to the external PHY Extended PHY control register #1 to set up the interface mode
Set up the MII Mgmt for a write cycle to the external PHY Mode control register to set up the interface mode selection.
Set up the MII Mgmt for a read cycle to PHY MII Mgmt register (write the PHY address and Register address),
set source clock divide by 14 for example to insure that MDC clock speed is not greater than 2.5 MHz
Assign a Physical address to the TBI so as to not conflict with the external PHY Physical address,
If auto-negotiation was enabled in the PHY, check to see if PHY has completed Auto-Negotiation.
The PHY Status register is at address 0x1 and in this case the PHY Address is 0x00.
Writing to MII Mgmt Control with 16-bit data intended for the external PHY register,
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
Write to MII Mgmt Control with 16-bit data intended for the external PHY register,
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-173. MII Mode Register Initialization Steps (continued)
the Management interface (overrides configuration signals of the PHY).
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0100]
MIIMCON[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMCON[0000_0000_0000_0000_00uu_00uu_0u00_0000]
MIIMCFG[1000_0000_0000_0000_0000_0000_0000_0111]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_0101]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_1100]
MIIMADD[0000_0000_0000_0000_0000_0000_0001_0111]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0000]
MIIMADD[0000_0000_0000_0000_0000_0000_0000_0001]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
TBIPA[0000_0000_0000_0000_0000_0000_0000_0101]
where u is user defined based on desired configuration.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY.
Perform an MII Mgmt write cycle to the external PHY
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
This indicates that the write cycle was completed.
Check to see if MII Mgmt write is complete.
Check to see if MII Mgmt write is complete
Check to see if MII Mgmt write is complete
Reset the management interface.
Setup the MII Mgmt clock speed,
Set to 05, for example.
selection.
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