MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1376

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
split-transaction data streams are managed with split-transaction isochronous transfer descriptors. All
interrupt, control, and bulk data streams are managed with queue heads and queue element transfer
descriptors. These data structures are optimized to reduce the total memory footprint of the schedule and
to reduce (on average) the number of memory accesses needed to execute a USB transaction.
Note that software must ensure that no interface data structure reachable by the EHCI host controller spans
a 4K-page boundary.
The data structures defined in this section are (from the host controller’s perspective) a mix of read-only
and read/writable fields. The host controller must preserve the read-only fields on all data structure writes.
21.5.1
Figure 21-34
(isochronous and interrupt). The periodic schedule is referenced from the operational registers space using
the PERIODICLISTBASE address register and the FRINDEX register. The periodic schedule is based on
an array of pointers called the periodic frame list. The PERIODICLISTBASE address register is combined
with the FRINDEX register to produce a memory pointer into the frame list. The periodic frame list
implements a sliding window of work over time.
Split transaction interrupt, bulk and control are also managed using queue heads and queue element
transfer descriptors.
The periodic frame list is a 4K-page aligned array of frame list link pointers. The length of the frame list
may be programmable. The programmability of the periodic frame list is exported to system software
through the HCCPARAMS register. If non-programmable, the length is 1024 elements. If programmable,
the length can be selected by system software as one of 256, 512, or 1024 elements. An implementation
must support all three sizes. Programming the size (that is, the number of elements) is accomplished by
system software writing the appropriate value into frame list size field in the USBCMD register.
21-42
Periodic Frame
PeriodicListBase
Operational
List Element
Registers
FRINDEX
Address
Periodic Frame List
shows the organization of the periodic schedule. This schedule is for all periodic transfers
1024, 512, or 256
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Elements
Figure 21-34. Periodic Schedule Organization
Periodic Frame List
•
•
•
Poll Rate: N –– > 1
•
•
•
A
A
A
A
A
A
Isochronous Transfer
Descriptor(s)
8
Interrupt Queue
A
4
Heads
• • •
Freescale Semiconductor
1
Last
Periodic has
End of
List Mark