MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1269

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If the link layer receives an XRDY primitive from the far end while it is in the partial or slumber state, it
returns to idle and signals a link sequence error to the command layer, that is, SError[S] = 1.
19.5.1.5
There are two separate scramblers used in the SATA controller, one for the data payload and the other for
repeated primitive suppression. The contents of each word of data (excluding all primitives) between SOF
and EOF must be scrambled before 8B/10B encoding. Scrambling is performed on word quantities
according to the following polynomial:
G(X) = X16 + X15 + X13 + X4 + 1
The scrambler is initialized with a seed value of 0xFFFF at each SOF transmission and rolls over every
2048 words. Payload data is scrambled prior to transmission, by XORing the data to be transmitted with
the output of this scrambler.
If a CONT primitive is transmitted, then the intervening data between the last CONT primitive and a
subsequent primitive must be scrambled also. This scrambler uses the same polynomial as defined above
for data payload scrambling and is reset to the initial value upon detection of a COMINIT or COMRESET
event. If a CONT primitive is transmitted or received during a frame transfer, then the current data payload
scrambler value at the last word is held.
When payload data is received by the link layer it is descrambled by XORing it with the output of its
descrambler. The descrambler is re-seeded at the beginning of the received data payload, that is, at each
SOF reception. The descrambler uses the same polynomial as the scrambler.
19.5.1.6
A 32-bit CRC is calculated on the data contents of each frame and is inserted in the word before the EOF.
The CRC covers all data bytes in the frame excluding any primitives such as SOF, EOF, HOLD, HOLDA,
DMAT, SYNC, X_RDY, R_RDY, or ALIGNs.
The CRC generator works on word quantities. Any padding to the boundary is done in the transport layer.
The polynomial used for the CRC is as follows:
The CRC is initialized with a seed value of 0x52325032 at each SOF.
The CRC generation or checking does not apply to primitives (as stated above) or to CONT’ed primitives.
If a CONT primitive is transmitted or received, then the intervening data between the last CONT primitive
and a subsequent primitive is not included in the CRC calculation for a frame. If this happens during a
frame transfer, then the current CRC scrambler value at the last word is held.
19.5.1.7
All data and primitives must be encoded prior to transmission on the line. The 8B/10B encode/decode
occur in the PHY layer.
Freescale Semiconductor
Frame Content Scrambler and Descrambler
CRC Generator and Checker
8B/10B Encode and Decode
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
G(X) = X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 +
X4 + X2 + X + 1
SATA Controller
19-39