MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 885

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.5.4.3.2
Figure 14-123
Table 14-132
Freescale Semiconductor
Offset 0x01
Reset 0
Bits
0–6
10
11
12
13
14
15
7
8
9
W
R
0
Remote
Extend
Extend
Status
Status
Name
Ability
Ability
Done
Fault
Link
0
Pre
AN
AN
No
—
—
—
0
describes the fields of the SR register.
describes the definition for the SR register.
Status Register (SR)
—
0
Reserved, should be cleared.
This bit indicates that PHY status information is also contained in the Register 15, Extended Status Register.
Returns 1 on read. This bit is read-only.
Reserved, should be cleared.
MF preamble suppression enable. This bit indicates whether or not the PHY is capable of handling MII
management frames without the 32-bit preamble field. Returns 1, indicating support for suppressed
preamble MII management frames. This bit is read-only.
Auto-negotiation complete. This bit is read-only and is cleared by default.
0 Either the auto-negotiation process is underway or the auto-negotiation function is disabled.
1 The auto-negotiation process has completed.
Remote fault. This bit is read-only and is cleared by default. Each read of the status register clears this bit.
0 Normal operation.
1 A remote fault condition was detected. This bit latches high in order for software to detect the condition.
Auto-negotiation ability. While read as set, this bit indicates that the PHY has the ability to perform
auto-negotiation. While read as cleared, this bit indicates the PHY lacks the ability to perform
auto-negotiation. Returns 1 on read. This bit is read-only.
Link status. This bit is read-only and is cleared by default.
0 A valid link is not established. This bit latches low allowing for software polling to detect a failure condition.
1 A valid link is established.
Reserved, should be cleared.
Extended capability. This bit indicates that the PHY contains the extended set of registers (those beyond
control and status). Returns 1 on read. This bit is read-only.
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
0
6
Extend
Status
1
Figure 14-123. Status Register Definition
7
Table 14-132. SR Descriptions
—
0
8
No Pre
1
9
AN Done
10
0
Description
Remote
Fault
11
0
Enhanced Three-Speed Ethernet Controllers
AN Ability
12
1
Status
Link
13
0
Access: Read only
—
14
0
Extend
Ability
15
14-137
1