MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1567

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The second type of threshold event is the quantity threshold event. For these types of threshold event
sequences the performance monitor counter is only incremented when the specified threshold event
exceeds the threshold value. These events do not use the multiplier register field (PMLCBn[TBMULT])
like the duration threshold events. This type of threshold event is generally used to monitor the usage of
buffers and queues. For example, the usage of a specific queue could be characterized by measuring the
amount of time the queue is completely full or partially full. For this example the threshold field would be
used to specify how many entries are required to be valid in the queue for that event to be counted.
24.4.4
By configuring one counter to increment each time another counter overflows, several counters can be
chained together to provide event counts larger than 32 bits. Each counter in a chain adds 32 bits to the
maximum count. The register chaining sequence is not arbitrary and is specified indirectly by selecting the
register overflow event to be counted. Selecting an event has the effect of selecting a source register
because all available chaining events, as shown in
Note that the chaining overflow event occurs when the counter reaches its maximum value and wraps, not
when the register’s msb is set. For this overflow to occur, PMLCAn[CE] should be cleared to avoid
signalling an interrupt when the counter’s most significant bit is set. Note that several cycles may be
required for the chained counters to reflect the true count because of the internal delay between when an
overflow occurs and a counter increments.
24.4.5
Triggering allows one counter to start or stop counting on the change of another counter or on the overflow
of another counter. More specifically, if PMC1 is set to start or stop counting as a result of a change or
overflow in counter PMC2, then counter PMC2 must be identified in the local control register of counter
Freescale Semiconductor
PMLCB n [THRESHOLD]
PMLCB n [TBMULT]
thresh_exceeded
perfmon_counter
thresh_counter
Chaining
Triggering
thresh_value
thresh_start
thresh_stop
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 24-9. Duration Threshold Event Sequence Timing Diagram
1
For this example a threshold value of three indicates that the user wishes to count the
number of times a particular event lasts three cycles or longer.
0
3
0
3
1
3
2
2
3
1
4
Table
5
1
24-10, are dedicated to specific registers.
6
3
7
2
8
9
1
10
Device Performance Monitor
2
3
11
2
12
1
24-13