MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1462

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Universal Serial Bus Interfaces
given endpoint and the given direction. In a functional stall condition, the device controller will continue
to return STALL responses to all transactions occurring on the respective endpoint and direction until the
endpoint stall bit is cleared by the DCD.
A protocol stall, unlike a function stall, is used on control endpoints is automatically cleared by the device
controller at the start of a new control transaction (setup phase). When enabling a protocol stall, the DCD
should enable the stall bits (both directions) as a pair. A single write to the ENDPTCTRLn register can
ensure that both stall bits are set at the same instant.
21.8.3.2
Data toggle is a mechanism to maintain data coherency between host and device for any given data pipe.
For more information on data toggle, refer to the Universal Serial Bus Revision 2.0 Specification.
21.8.3.2.1
The DCD may reset the data toggle state bit and cause the data toggle sequence to reset in the device
controller by writing a '1' to the data toggle reset bit in the ENDPTCTRLn register. This should only be
necessary when configuring/initializing an endpoint or returning from a STALL condition.
21.8.3.2.2
This feature is for test purposes only and should never be used during normal device controller operation.
Setting the data toggle Inhibit bit active ('1') causes the USB controller to ignore the data toggle pattern
that is normally sent and accept all incoming data packets regardless of the data toggle state.
In normal operation, the USB controller checks the DATA0/DATA1 bit against the data toggle to determine
if the packet is valid. If Data PID does not match the data toggle state bit maintained by the device
controller for that endpoint, the Data toggle is considered not valid. If the data toggle is not valid, the
device controller assumes the packet was already received and discards the packet (not reporting it to the
21-128
SETUP packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
IN/OUT/PING packet received by a non-control endpoint
SETUP packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
IN/OUT/PING packet received by a control endpoint
Data Toggle
Any write to the ENDPTCTRLn register during operational mode must
preserve the endpoint type field (that is, perform a read-modify-write).
Data Toggle Reset
Data Toggle Inhibit
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 21-84. Device Controller Stall Response Matrix
USB Packet
NOTE
Endpoint
Stall Bit.
N/A
N/A
'1
'0
'1
'0
STALL Bit.
Effect on
Cleared
None
None
None
None
None
ACK/NAK/NYET
ACK/NAK/NYET
Freescale Semiconductor
USB Response
STALL
STALL
STALL
ACK