MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 23

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
13.5.1.1
13.5.1.2
13.5.1.3
13.5.2
13.5.2.1
13.5.2.2
13.5.2.3
13.5.2.4
13.5.3
13.5.4
13.5.4.1
13.5.4.2
13.5.4.3
13.5.4.4
13.5.4.5
13.5.4.6
13.5.5
13.5.6
14.1
14.2
14.3
14.4
14.4.1
14.5
14.5.1
14.5.2
14.5.3
14.5.3.1
14.5.3.1.1
14.5.3.1.2
14.5.3.1.3
14.5.3.1.4
14.5.3.1.5
14.5.3.1.6
14.5.3.1.7
14.5.3.1.8
14.5.3.1.9
Freescale Semiconductor
Overview........................................................................................................................ 14-1
Features .......................................................................................................................... 14-2
Modes of Operation ....................................................................................................... 14-5
External Signals Description ......................................................................................... 14-6
Memory Map/Register Definition ............................................................................... 14-14
Bus Turnaround ....................................................................................................... 13-92
Interface to Different Port-Size Devices.................................................................. 13-93
Command Sequence Examples for NAND Flash EEPROM................................... 13-95
Interfacing to Fast-Page Mode DRAM Using UPM ............................................... 13-99
Interfacing to ZBT SRAM Using UPM................................................................. 13-104
Detailed Signal Descriptions ..................................................................................... 14-9
Top-Level Module Memory Map ............................................................................ 14-15
Detailed Memory Map............................................................................................. 14-15
Memory-Mapped Register Descriptions.................................................................. 14-26
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Multiplexed Address/Data Bus for 32-Bit Addressing........................................ 13-90
Peripheral Hierarchy on the Local Bus for High Bus Speeds ............................. 13-91
GPCM Timings.................................................................................................... 13-92
Address Phase after Previous Read ..................................................................... 13-93
Read Data Phase after Address Phase ................................................................. 13-93
Read-Modify-Write Cycle for Parity Protected Memory Banks ......................... 13-93
UPM Cycles with Additional Address Phases..................................................... 13-93
NAND Flash Soft Reset Command Sequence Example ..................................... 13-95
NAND Flash Read Status Command Sequence Example ................................... 13-96
NAND Flash Read Identification Command Sequence Example ....................... 13-96
NAND Flash Page Read Command Sequence Example ..................................... 13-97
NAND Flash Block Erase Command Sequence Example .................................. 13-97
NAND Flash Program Command Sequence Example ........................................ 13-98
eTSEC General Control and Status Registers...................................................... 14-26
Controller ID Register (TSEC_ID).................................................................. 14-26
Controller ID Register (TSEC_ID2)................................................................ 14-27
Interrupt Event Register (IEVENT) ................................................................ 14-27
Interrupt Mask Register (IMASK) .................................................................. 14-31
Error Disabled Register (EDIS)....................................................................... 14-33
Ethernet Control Register (ECNTRL) ............................................................. 14-35
Pause Time Value Register (PTV) ................................................................... 14-37
DMA Control Register (DMACTRL) ............................................................. 14-38
TBI Physical Address Register (TBIPA) ......................................................... 14-40
Enhanced Three-Speed Ethernet Controllers
Contents
Chapter 14
Title
Number
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