MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 492

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
10.7.1.5
The AESU reset control register has three self-clearing bits, where each bit corresponds to a different type
of AESU reset.
10.7.1.6
The AESU status register is a read-only register that reflects the state of six status outputs. Writing to this
location results in an address error being reflected in the AESU interrupt status register.
10-62
Offset 0x3_4018
Reset
0–60
W
Bits
R
61
62
63
0
ECB, CBC
OFB, CMAC, SRT, CCM,
XCBC-MAC, CFB128
XTS
GCM
XOR
AESU Cipher Mode
AESU Reset Control Register
AESU Status Register
Names
Figure 10-24
SR
MI
—
RI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-25. AESU Reset Control Register Field Descriptions
Reserved
Reset Interrupt. Setting this bit resets the AESU’s done and error interrupts, and resets the
state of the AESU interrupt status register.
0 Do not reset
1 Reset interrupt logic
Module Initialization. The same as software reset (including the initialization routine: see
SR bit description below), except that the interrupt mask register remains unchanged.
0 Do not reset
1 Reset most of AESU
Software reset. Functionally equivalent to hardware reset, but applies only to AESU. All
registers and internal state are returned to their defined reset states. The RESET_DONE
bit in the AESU status register indicates when this initialization routine is complete
0 Do not reset
1 Full AESU reset
shows the AESU reset control register, and
Figure 10-24. AESU Reset Control Register
Table 10-24. Use of Data Size Register
lowest 7 bits [57:63]
all bits
all bits
all bits
Register bits used by SEC
(others are don’t cares)
—
All zeros
Description
must be a multiple of 128
must be a multiple of 8
must be a multiple of 8, minimum 128
any value
must be a multiple of 256
(data size in bits)
Table 10-25
Legal Values
60
Freescale Semiconductor
describes its fields.
Access: Read/Write
RI
61
MI
62
SR
63