MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 419

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 9-40
9.3.8.2
There is one CTPR per processor core on this device as shown in
Software must write the priority of the current processor core task in the CTPR for each core. The PIC uses
this value for comparison with the priority of incoming interrupts. Given several concurrent incoming
interrupts, the highest priority interrupt is asserted to that core if the following apply:
Table 9-46
Freescale Semiconductor
0–29
Bits Name
28–31 TASKP Task priority. Indicates the threshold that individual interrupt priorities must exceed for the interrupt request to
30
31
0–27
Bits
•
•
P1
P0
—
The interrupt is not masked.
The priority of the interrupt is higher than the values in the corresponding CTPR[TASKP] and ISR.
Name
Offset CTPR0: 0x0080; CTPR1
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
—
W
describes the IPIDRn fields.
describes the CTPR task priority field.
R
Reserved, should be cleared.
Processor core 1. Specifies if processor core 1 receives the interrupt. This interrupt is multicasting, so both P0 and
P1 can be set.
0 Processor core 1 does not receive the interrupt
1 Directs the interrupt to processor core 1
Note: Reserved in single-processor implementations.
Processor core 0. Determines if processor core 0 receives the interrupt.
0 Processor core 0 does not receive the interrupt.
1 Directs the interrupt to processor core 0.
Processor Core Current Task Priority Registers 0–1 (CTPR0–CTPR1)
1
Reserved, should be cleared.
be serviced.
0000–1111 x VPR n [PRIORITY] must exceed this value for the interrupt request to be serviced. Note the
0000 Lowest priority. All interrupts except those whose priority are 0 can be serviced.
1111 Highest priority. No interrupts are signaled to that processor core. Hardware selects this value on a
0
CTPR has meaning only for interrupts routed to int.
Reserved in single-processor implementations.
Figure 9-46. Processor Core Current Task Priority Registers (CTPR n )
following special cases:
device hard reset or when the corresponding PIR[P n ] is set.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 9-46. CTPR n Field Descriptions
Table 9-45. IPIDR n Field Descriptions
1
0x1080; Pre-CPU offset: 0x0080
NOTE
—
Description
Description
Figure
9-46.
Programmable Interrupt Controller (PIC)
Access: Read/Write
27 28
TASKP
31
9-49