MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1196

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
format of general data structures. Provided that software is aware of the endianness and format of the data
structure, it can correctly interpret the data on either side of the bridge.
Figure 17-125
address invariant bridge to a little endian destination.
Note that although the significance of the bytes within the scalar have changed, the address of the
individual bytes that make up the scalar have not changed. As long as software is aware that the source of
the data used a big endian format, the data can be interpreted correctly.
Figure 17-127
Figure 17-127
invariance.
17-100
Address lsbs
Significance
Byte lane
Data
Address lsbs
Address lsbs
Significance
Significance
Byte lane
Byte lane
Data
Data
shows an outbound transfer of an 8-byte scalar, 0x5455_1617_CDCE_2728, using address
shows the transfer of a 4-byte scalar, 0x4142_4344, from a big endian source across an
shows data flowing the other way, from a little endian source to a big endian destination.
MSB
000
54
0
Figure 17-125. Address Invariant Byte Ordering—4 bytes Outbound
Figure 17-127. Address Invariant Byte Ordering—8 bytes Outbound
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 17-126. Address Invariant Byte Ordering—4 bytes Inbound
001
55
1
Big endian source bus
010
16
2
MSB
MSB
000
011
41
41
0
3
011
17
Little endian
source bus
source bus
3
Big endian
001
010
42
42
1
2
CD CE
100
4
010
001
43
43
2
1
101
5
LSB
LSB
011
000
44
44
3
0
110
27
6
LSB
111
28
7
MSB
111
28
7
MSB
MSB
011
000
44
44
3
0
destination bus
destination bus
Little endian destination bus
110
27
Little endian
6
Big endian
010
001
43
43
2
1
101
CE CD
5
001
010
42
42
1
2
100
4
LSB
LSB
000
011
41
41
0
3
011
17
3
010
16
2
Freescale Semiconductor
001
55
1
LSB
000
54
0