MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 7

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
5.1
5.2
5.3
5.3.1
6.1
6.1.1
6.2
6.2.1
6.2.2
6.2.3
6.3
6.3.1
6.3.1.1
6.3.1.2
6.3.1.2.1
6.3.1.2.2
6.3.1.2.3
6.3.1.3
6.3.1.3.1
6.3.1.3.2
6.3.1.4
6.3.1.4.1
6.3.1.4.2
6.4
6.4.1
6.5
6.6
6.6.1
6.6.2
Freescale Semiconductor
e500 Core Overview ........................................................................................................ 5-1
e500 Core Integration and the Core Complex Bus (CCB) .............................................. 5-3
Summary of Core Integratation Details ........................................................................... 5-4
L2 Cache Overview ......................................................................................................... 6-1
L2 Cache and SRAM Organization ................................................................................. 6-4
Memory Map/Register Definition ................................................................................... 6-8
External Writes to the L2 Cache (Cache Stashing)........................................................ 6-25
L2 Cache Timing ........................................................................................................... 6-27
L2 Cache and SRAM Coherency................................................................................... 6-27
Processor Version Register (PVR) and System Version Register (SVR) .................... 5-6
L2 Cache and SRAM Features .................................................................................... 6-2
Accessing the On-Chip Array as an L2 Cache ............................................................ 6-5
Accessing the On-Chip Array as an SRAM ................................................................ 6-5
Connection of the On-Chip Memory to the System .................................................... 6-7
L2/SRAM Register Descriptions ............................................................................... 6-10
Stash-Only Cache Regions ........................................................................................ 6-26
L2 Cache Coherency Rules........................................................................................ 6-28
Memory-Mapped SRAM Coherency Rules .............................................................. 6-29
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
L2 Control Register (L2CTL)................................................................................ 6-10
L2 Cache External Write Registers ....................................................................... 6-13
L2 Memory-Mapped SRAM Registers ................................................................. 6-15
L2 Error Registers.................................................................................................. 6-17
L2 Cache External Write Address Registers 0–3 (L2CEWARn) ...................... 6-13
L2 Cache External Write Address Registers Extended Address 0–3
L2 Cache External Write Control Registers 0–3 (L2CEWCRn)....................... 6-14
L2 Memory-Mapped SRAM Base Address Registers 0–1 (L2SRBARn) ........ 6-16
L2 Memory-Mapped SRAM Base Address Registers Extended Address 0–1
Error Injection Registers.................................................................................... 6-18
Error Control and Capture Registers ................................................................. 6-20
(L2CEWAREAn)........................................................................................... 6-14
(L2SRBAREAn)............................................................................................ 6-17
e500 Core Complex and L2 Cache
e500 Core Integration Details
L2 Look-Aside Cache/SRAM
Contents
Chapter 5
Chapter 6
Part II
Title
Number
Page
vii