MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 433

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.1
bottleneck normally associated with slave-only cores. A host processor accesses the SEC through its
device drivers using system memory for data storage. The SEC resides in the peripheral memory map of
the processor. When an application requires cryptographic functions, it creates descriptors for the SEC
which define the functions to be performed and the locations of the data (descriptors are introduced in
Section 10.1.1, “Descriptor
single 64-bit write, the host processor can enqueue a descriptor pointer in the SEC. The SEC’s
bus-mastering capability then enables it to execute the entire cryptographic task, performing reads and
writes on system memory as needed.
A block diagram of the SEC internal architecture is shown in
The SEC interfaces with the system buses through the controller (the controller is introduced in
Section 10.1.3, “Controller
interface permits an external device to perform 32- or 64-bit writes on any register or FIFO inside the SEC
Some locations permit byte writes. Reads may be of any length. Using the master interface, the controller
can transfer blocks of 64-bit words between system memory and SEC FIFOs or registers.
A typical SEC operation begins when a host processor writes a descriptor pointer to the fetch FIFO in one
of the four SEC virtual channels. This write operation uses the slave interface (where the host is master
Freescale Semiconductor
The SEC can act as a master on the internal system bus, allowing it to offload the data movement
•
— Supports scatter/gather of input and output data (where the term data is used loosely, and
— Masters data bursts on 32-byte boundaries to optimize bus throughput
Master and slave interfaces, with DMA capability
— 32- or 36-bit address/64-bit data
— Master interface allows pipelined requests
— DMA data blocks can start and end on any byte boundary
Slave
Interface
SEC Architecture Overview
(4 virtual channels)
includes keys, context, ICV values, etc.), enabling concatenation of multiple segments of
memory when reading or writing data
Polychannel
System Bus
Controller
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Master
Interface
Overview”, and discussed in detail in
Internal
Bus
Overview”, and discussed in detail in
Figure 10-1. SEC Functional Modules
PKEU
RNGU
FIFO
DEU
FIFO
FIFO
Execution Units (EUs)
AESU
Figure
FIFO
FIFO
Section 10.5,
Section 10.3,
10-1.
AFEU
FIFO
FIFO
KEU
FIFO
FIFO
“Controller”). The slave
“Descriptors”). With a
MDEU
Security Engine (SEC) 3.0
FIFO
CRCU
FIFO
10-3