MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 776

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
Each eTSEC can issue three kinds of hardware interrupt to the PIC:
Some of the error interrupts are independently counted in the MIB block counters. Software may choose
to mask off these interrupts because these errors are visible to network management through the MIB
counters.
Figure 14-4
14-28
Offset eTSEC1:0x2_4010;
Reset
Reset
W
W
1. Transmit data frame interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and
2. Receive data frame interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and
3. Error, diagnostic, and special interrupts—Issued whenever bits MAG, GTSC, GRSC, TXC, RXC,
R BABR
R
eTSEC3:0x2_6010
RXB
either transmit interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for TXF. To negate this hardware interrupt, software must clear both TXB and TXF bits.
either receive interrupt coalescing is disabled or the interrupt coalescing thresholds have been met
for RXF. To negate this hardware interrupt, software must clear both RXB and RXF bits.
BABR, BABT, LC, CRL, FGPI, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN, BSY, MSRO,
MMRD, or MMRW of IEVENT are set to 1. Software must clear all of these bits to negate an
error/diagnostic/special hardware interrupt.
— Magic Packet reception event is: MAG
— Operational diagnostics are events on: GTSC, GRSC, TXC, and RXC
— Interrupts resulting from errors/problems detected in the network or transceiver are: BABR,
— Interrupts resulting from internal or combination errors are: FIR, FIQ, DPE, PERR, EBERR,
— Special function interrupts are: FGPI, MSRO, MMRD, and MMRW
w1c
w1c
16
0
BABT, LC, and CRL
TXE, XFUN, and BSY
describes the definition for the IEVENT register.
RXC
w1c
17
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
BSY
w1c
2
—
EBERR
w1c
19
3
Figure 14-4. IEVENT Register Definition
MAG MMRD MMWR GRSC RXF
w1c
—
20
4
MSRO
w1c
w1c
21
5
GTSC
w1c
w1c
All zeros
All zeros
22
6
BABT TXC TXE TXB TXF
w1c
w1c
23
7
w1c
w1c
24
8
w1c
25
9
—
w1c w1c
10
26
FGP
w1c w1c w1c w1c
11
27
I
Freescale Semiconductor
FIR FIQ DPE PERR
—
12
28
w1c w1c
LC CRL XFUN
13
29
Access: w1c
14
30
w1c
w1c
15
31