MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1667

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.3.1.15, 13-33
13.4.2, 13-49
13.5.1.1
13.5.4.4, 13-98
13.5.4.5, 13-98
13.5.4.6, 13-99
14.2, 14-4
14.5.3.1.3, 14-30
14.5.3.1.6, 14-35
Freescale Semiconductor
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Corrected the LBCR[AHD] field state description as follows:
0
platform clock period prior to the address being invalidated. For instance, at
33.3 MHz, this provides 3 ns of additional address hold time at the external
address latch.
1
platform clock period prior to the address being invalidated. This halves the
address hold time, but extends the latch enable duration. This may be necessary
for very high frequency designs.
Corrected Figure 13-33 so that LAD[0:31] of the eLBC comes out and [12:26]
goes to the Latch and then connects to A[19:5] in the Memory/Peripheral.
Removed section
Corrected phrase ‘The sequence is initiated by writing FMR[OP] = 10’ to read
‘The sequence is initiated by writing FMR[OP]=11’
Corrected phrase ‘The sequence is initiated by writing FMR[OP] = 10’ to read
‘The sequence is initiated by writing FMR[OP]=11’
Corrected phrase ‘The sequence is initiated by writing FMR[OP] = 10’ to read
‘The sequence is initiated by writing FMR[OP]=11’
Added clarification to 1588 features bullet item as follows:
(1588 not supported in conjunction with SGMII 10/100)
Changed second sentence of IEVENT[CRL] field description from:
The frame is discarded without being transmitted and transmission of the next
frame commences.
to:
The frame is discarded without being transmitted and the queue halts
(TSTAT[THLTn] set to 1).”
Updated ECNTRL[CLRCNT] field description to read as follows:
Clear all statistics counters and carry registers.
0
indicators.
1
This bit is self-resetting.
Updated ECNTRL[AUTOZ] field description to read as follows:
Automatically zero MIB counter values and carry registers.
0
1
read.
This is a steady state signal and must be set prior to enabling the Ethernet
controller and must not be changed without proper care.
During address phases on the local bus, the LALE signal negates one
During address phases on the local bus, the LALE signal negates 0.5
Allow MIB counters to continue to increment and keep any overflow
Reset all MIB counters and CAR1 and CAR2.
The user must write the addressed counter zero after a host read.
The addressed counter value is automatically cleared to zero after a host
Revision History
B-3