MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 420

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Programmable Interrupt Controller (PIC)
9.3.8.3
The processor core WHOAMIn register, shown in
determine its physical connection to the PIC. The value returned when reading this register may be used
to determine the value for the destination masks used for dispatching interrupts.
Table 9-47
9.3.8.4
In systems based on processors built on Power Architecture™ technology, the interrupt acknowledge
function occurs as an explicit read operation to a memory-mapped interrupt acknowledge register (IACK),
shown in
interrupt vector corresponding to the highest priority pending interrupt. Reading IACK also has the
following side effects:
Reading IACK when no interrupt is pending returns the spurious vector value, as described in
Section 9.3.1.8, “Spurious Vector Register (SVR).”
9-50
Offset WHOAMI: 0x0090; WHOAMI1
Reset 0
•
•
•
27–31
0–26
W
Bits
R
The associated field in the corresponding interrupt pending register (IPR) is cleared for
edge-sensitive interrupts. See
The corresponding in-service register (ISR) is updated.
The corresponding int output signal from the PIC is negated.
1
0
Figure
Reserved in single-processor implementations.
Name
0
describes the WHOAMIn fields.
—
ID
Who Am I Registers 0–1 (WHOAMI0–WHOAMI1)
Processor Core Interrupt Acknowledge Registers 0–1 (IACK0–IACK1)
0
IACK has meaning only for interrupts routed to int and should not be
accessed for interrupts routed to cint or IRQ_OUT.
9-48. Each processor core has an IACK register assigned to it. Reading IACK returns the
Reserved, should be cleared.
Returns the ID of the processor core reading this register.
0_0000 Processor core 0
0_0001 Processor core 1. (Value not supported in single-processor implementations.)
1_1111 Other devices
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0
Figure 9-47. Processor Core Who Am I Registers (WHOAMI n )
0
0
0
Table 9-47. WHOAMI n Field Descriptions
0
1
: 0x1090; Per-CPU offset: 0x0090
0
Section 9.4.1.2, “Interrupts Routed to int.”
0
0
0
—
0
NOTE
Figure
0
0
Description
0
9-47, can be read by a processor core to
0
0
0
0
0
0
0
0
Freescale Semiconductor
0
26 27 28 29 30 31
0
Access: Read only
n n
ID
n
n n