MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1220

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Serial Peripheral Interface
18.3.1
18.3.1.1
The eSPI mode register (SPMODE), shown in
Table 18-4
18.3.1.2
The eSPI event register (SPIE) generates interrupts and reports events recognized by the eSPI. When an
event is recognized, the eSPI sets the corresponding SPIE bit. Clear SPIE bits by writing a 1—writing 0
has no effect. Setting a bit in the eSPI mask register (SPIM) enables and clearing a bit masks the
corresponding interrupt. Unmasked SPIE bits must be cleared before the core clears internal interrupt
requests. Bits RNE and TNF are status bits. Fields RXCNT and TXCNT hold Rx and Tx fifos statuses.
They are not cleared as a result of writing to SPIE.
18-6
Offset 0x000
Reset 0
18–23
27–31
2–17
Bits
W
R
0
1
EN LOOP
0
RXTHR Rx FIFO threshold—if Rx FIFO has more than RXTHR bytes, an interrupt can be issued to the core.
TXTHR Tx FIFO threshold—if Tx FIFO has less than TXTHR bytes, an interrupt can be issued to the core.
LOOP
Name
describes the SPMODE fields.
Register Descriptions
0
1
EN
—
eSPI Mode Register (SPMODE)
eSPI Event Register (SPIE)
0
2
Enable eSPI. Any bits in SPMODE must not change when EN is set.
0 The eSPI is disabled. The eSPI is in a idle state and consumes minimal power. The eSPI BRG is not
1 The eSPI is enabled.
Loop mode. Enables local loopback operation.
0 Normal operation.
1 Loopback mode. Used to test the eSPI controller internal functionality, the transmitter output is
Reserved
Valid values: 1–32
Valid values: 0–31
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
functioning and the input clock is disabled.
internally connected to the receiver input. The receiver and transmitter operate normally, except that
received data is ignored.
Figure 18-3. eSPI Mode Register (SPMODE)
Table 18-4. SPMODE Field Descriptions
—
Figure
18-3, controls eSPI general operation mode.
Description
17 18
0
0
TXTHR
0
0
0
23 24
0
0
Freescale Semiconductor
—
0
Access: Read/Write
26 27
0
0 1 1 1 1
RXTHR
31