MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 800

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.2.11 Transmit Descriptor Base Address Registers (TBASE0–TBASE7)
The TBASEn registers are written by the user with the base address of each TxBD ring n. Each such value
must be divisible by eight, since the three least significant bits always write as 000.
the definition for the TBASEn registers.
Table 14-26
14.5.3.2.12 Transmit Time Stamp Identification Register (TMR_TXTS1–2_ID)
Transmit time stamp identification register (TMR_TXTSn_ID). This register holds the identification
number of the transmitted frame corresponding to the timestamp captured in TMR_TXTSn_H/L. Each
time the eTSEC is instructed to capture the timestamp of an outgoing frame via TxFCB[PTP] the
associated field in TxFCB[PTP_ID] is stored in this register, overwriting the previous value.
This register is read only in normal operation.
TMR_TXTSn_ID register.
14-52
29–31
Offset eTSEC1:0x2_4280+4 n;
Reset
0–28 TBASE n Transmit base for ring n . TBASE defines the starting location in the memory map for the eTSEC TxBDs. This
Bits
Offset eTSEC1:0x2_4204+8 n ;
Reset
W
R
W
eTSEC3:0x2_6280+8 n
R
0
Name
eTSEC3:0x2_6204+8 n
—
0
describes the fields of the TBASEn registers.
field must be 8-byte aligned. Together with setting the W (wrap) bit in the last BD, the user can select how many
BDs to allocate for the transmit packets. The user must initialize TBASE before enabling the eTSEC transmit
function on the associated ring.
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-26. TBASE0–TBASE7 Field Descriptions
Figure 14-22. TMR_TXTS n _ID Register Definition
—
Figure 14-21. TBASE Register Definition
Figure 14-22
TBASE n
All zeros
All zeros
15 16
Description
describes the definition for the
TXTS_ID
Figure 14-21
Freescale Semiconductor
Access: Read/Write
Access: Read only
28 29
describes
—
31
31