MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 364

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DDR Memory Controller
8-90
ODT_WR_CFG
ODT_PD_EXIT
ODT_RD_CFG
PRETOACT
ACTTOPRE
ACTTORW
Parameter
CASLAT
Table 8-69. Programming Differences Between Memory Types (continued)
Chip Select ODT Read
Configuration
Chip Select ODT Write
Configuration
ODT Powerdown Exit
Precharge to Activate
Timing
Activate to Precharge
Timing
Activate to Read/Write
Timing
CAS Latency
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Description
DDR2
DDR3
DDR2
DDR3
DDR3
DDR2
DDR3
DDR2
DDR3
DDR2
DDR3
DDR3
DDR2
DDR2
could be set differently depending on system
topology. However, systems with only 1 chip select
will typically not use ODT when issuing reads to
the memory.
could be set differently depending on system
topology. However, systems with only 1 chip select
typically do not use ODT when issuing reads to
the memory.
could be set differently depending on system
topology. However, ODT will typically be set to
assert for the chip select that is getting written to
(value would be set to 001).
could be set differently depending on system
topology. However, ODT typically is set to assert
for the chip select that is getting written to (value
would be set to 001).
specifications for the memory used. The JEDEC
parameter this applies to is t
Should be set to 0001 for DDR3. The powerdown
times (t
controlled via TIMING_CFG_0[ACT_PD_EXIT]
and TIMING_CFG_0[PRE_PD_EXIT].
the memory used (t
the memory used (t
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
Should be set, along with the Extended Activate to
Precharge Timing, according to the specifications
for the memory used (t
the memory used (t
the memory used (t
Latency, to the desired CAS latency
Should be set, along with the Extended CAS
Latency, to the desired CAS latency
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Can be enabled to assert ODT if desired. This
Should be set according to the DDR2
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set according to the specifications for
Should be set, along with the Extended CAS
XP
and t
Differences
XPDLL
RP
RP
RCD
RCD
) required for DDR3 are
)
)
RAS
RAS
)
)
)
)
AXPD
.
Freescale Semiconductor
Section/page
8.4.1.2/8-13
8.4.1.2/8-13
8.4.1.5/8-17
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19
8.4.1.6/8-19