MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 828

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.5.3.5.5
The MAXFRM register is written by the user.
Table 14-47
14.5.3.5.6
The MIIMCFG register is written by the user to configure all MII management operations. Note that MII
management hardware is shared by all eTSECs. Thus, only through the MIIM registers of eTSEC1 can
external PHYs be accessed and configured. Note: when an eTSEC is configured to use TBI/RTBI,
configuration of the TBI/RTBI (described in
the MIIM registers for that eTSEC. For example, if a TBI/RTBI interface is required on eTSEC2, then the
MIIM registers starting at offset 0x2_5520 are used to configure it.
Figure 14-44
14-80
16–31 Maximum Frame This field is set to 0x0600 (1536 bytes) by default and always must be set to a value greater than or
0–15
Bits
Offset
Reset 0
Offset eTSEC1:0x2_4520
Reset
W
R
W
R
0
Reset Mgmt
Name
0
describes the fields of the MAXFRM register.
describes the definition for the MIIMCFG register.
—
0
0
Maximum Frame Length Register (MAXFRM)
MII Management Configuration Register (MIIMCFG)
0
eTSEC1:0x2_4510;
0
eTSEC3:0x2_6510
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 14-44. MII Management Configuration Register Definition
0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Reserved
equal to 0x0040 (64 bytes), but not greater than 0x2580 (9600 bytes). It sets the maximum Ethernet
frame size in both the transmit and receive directions. (Refer to MACCFG2[Huge Frame].) It does
not affect the size of packets sent or received via the FIFO packet interface.
Note that if MACCFG2[Huge Frame] = 0, the value of this field must be less than or equal to
MRBLR[MRBL]
Configuration 2 Register
Register
Figure 14-43. Maximum Frame Length Register Definition
0
0
(MRBLR),” and
0
—
Table 14-47. MAXFRM Field Descriptions
0
0
(minimum number of RxBDs per ring). See
0
0
Section 14.6.8.3, “Receive Buffer Descriptors
(MACCFG2),”
Section 14.5.4, “Ten-Bit Interface
0
Figure 14-43
0
0
—
15 16
0
Section 14.5.3.3.9, “Maximum Receive Buffer Length
0
Description
shows the MAXFRM register.
0
0
0
0
1
Section 14.5.3.5.2, “MAC
Maximum Frame
1
0
(TBI)”) is done through
(RxBD).”
0
26
0
Freescale Semiconductor
0
No Pre — MgmtClk
27
0
0
Access: Read/Write
Access: Read/Write
0
28 29
0
0
1
0
1
0
31
31
0
1