MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1323

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.6.3.1.1
During block write (CMD24–27), one or more blocks of data are transferred from the host to the card with
a CRC appended to the end of each block by the host. If the CRC fails, the card should indicate the failure
on the SDHC_DAT line (see below). The transferred data is discarded and not written, and all further
transmitted blocks (in multi-block write mode) are ignored.
If the host uses partial blocks whose accumulated length is not block-aligned and block misalignment is
not allowed (CSD parameter WRITE_BLK_MISALIGN is not set), the card detects the block
misalignment error and aborts programming before the beginning of the first misaligned block. The card
sets the ADDRESS_ERROR error bit in the status register, defined in the MMC/SD Specification, and
then waits in the receive-data state for a stop command while ignoring all further data transfers. The write
operation is also aborted if the host attempts to write over a write-protected area.
For MMC and SD cards, programming the CID and CSD registers does not require a previous block length
setting. The transferred data is also CRC protected. If a part of the CSD or CID register is stored in the
ROM, this unchangeable section must match the corresponding section of the receive buffer. If this match
fails, then the card reports an error and does not change any register contents.
Some cards may require a long and unpredictable period of time to write a block of data. After receiving
a block of data and completing the CRC check, the card begins writing. If its write buffer is full and unable
to accept new data from a new WRITE_BLOCK command, the card holds the SDHC_DAT line low. The
host may poll the status of the card with a SEND_STATUS command (CMD13) cards, at any time and the
card responds with its status. The card status indicates whether the card can accept new data or if the write
process is still in progress. The host may deselect the card by issuing CMD7 (to select a different card) to
change the card into the standby state and release the SDHC_DAT line without interrupting the write
operation. When re-selecting the card, it reactivates the busy indication by pulling SDHC_DAT low if
programming is still in progress and the write buffer is unavailable.
For simplicity, the software flow described below incorporates the internal DMA, and the write operation
is a multi-block write with Auto CMD12 enabled. For the other method (CPU polling status) and different
transfer nature, the internal DMA part of the procedure should be removed and alternative steps inserted.
Freescale Semiconductor
1. Check the card status and wait until the card is ready for data.
2. Set the card block length.
3. Set eSDHC BLKATTR[BLKSIZE] to the same as the block length set in the card in step 2.
4. Set eSDHC BLKATTR[BLKCNT] with the number of blocks to send.
5. Disable the buffer write ready interrupt, configure the DMA setting, and enable the eSDHC DMA
6. Wait for the transfer complete interrupt.
7. Check the status bit to see if a read CRC error or any other errors occurred between sending Auto
— MMC/SD cards — use SET_BLOCKLEN (CMD16)
when sending the command with data transfer. Set XFERTYP[AC12EN].
CMD12 and receiving the response.
Normal Write
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Enhanced Secure Digital Host Controller
20-49