MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 5

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
3.1
3.2
3.3
4.1
4.2
4.2.1
4.2.2
4.3
4.3.1
4.3.1.1
4.3.1.1.1
4.3.1.1.2
4.3.1.2
4.3.1.2.1
4.3.1.2.2
4.3.1.3
4.3.1.3.1
4.3.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.2
4.4.3
4.4.3.1
4.4.3.2
4.4.3.3
4.4.3.4
4.4.3.5
4.4.3.6
4.4.3.7
4.4.3.8
4.4.3.9
Freescale Semiconductor
Signals Overview ............................................................................................................. 3-1
Configuration Signals Sampled at Reset ....................................................................... 3-15
Output Signal States During Reset ................................................................................ 3-17
Overview.......................................................................................................................... 4-1
External Signal Descriptions ........................................................................................... 4-1
Memory Map/Register Definition ................................................................................... 4-3
Functional Description..................................................................................................... 4-8
System Control Signals................................................................................................ 4-2
Clock Signals ............................................................................................................... 4-3
Local Configuration Control........................................................................................ 4-4
Boot Sequencer ............................................................................................................ 4-8
Reset Operations .......................................................................................................... 4-8
Power-On Reset Sequence........................................................................................... 4-9
Power-On Reset Configuration.................................................................................. 4-11
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Accessing Configuration, Control, and Status Registers......................................... 4-4
Accessing Alternate Configuration Space ............................................................... 4-5
Boot Page Translation.............................................................................................. 4-7
Soft Reset................................................................................................................. 4-8
Hard Reset ............................................................................................................... 4-8
System PLL Ratio.................................................................................................. 4-11
e500 Core PLL Ratio ............................................................................................. 4-12
DDR PLL Ratio Configuration.............................................................................. 4-13
System Speed Configuration ................................................................................. 4-13
Core Speed Configuration ..................................................................................... 4-14
Boot ROM Location .............................................................................................. 4-14
Host/Agent Configuration ..................................................................................... 4-15
SerDes1 I/O Port Selection.................................................................................... 4-16
SerDes2 I/O Port Selection.................................................................................... 4-17
Updating CCSRBAR ........................................................................................... 4-4
Configuration, Control, and Status Registers Base Address
Alternate Configuration Base Address Register (ALTCBAR)............................ 4-6
Alternate Configuration Attribute Register (ALTCAR)...................................... 4-6
Boot Page Translation Register (BPTR).............................................................. 4-7
Register (CCSRBAR)...................................................................................... 4-5
Reset, Clocking, and Initialization
Signal Descriptions
Contents
Chapter 3
Chapter 4
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Number
Page
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