MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 45

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
21.6.10.1
21.6.10.2
21.6.10.3
21.6.11
21.6.12
21.6.12.1
21.6.12.1.1
21.6.12.1.2
21.6.12.2
21.6.12.2.1
21.6.12.2.2
21.6.12.2.3
21.6.12.2.4
21.6.12.2.5
21.6.12.2.6
21.6.12.2.7
21.6.12.2.8
21.6.12.2.9
21.6.12.3
21.6.12.3.1
21.6.12.3.2
21.6.12.3.3
21.6.12.3.4
21.6.12.3.5
21.6.12.3.6
21.6.12.3.7
21.6.13
21.6.14
21.6.14.1
21.6.14.1.1
21.6.14.1.2
21.6.14.1.3
21.6.14.1.4
21.6.14.1.5
21.6.14.2
21.6.14.2.1
21.6.14.2.2
21.6.14.2.3
21.6.14.2.4
21.7
21.7.1
Freescale Semiconductor
Device Data Structures .............................................................................................. 21-116
Ping Control............................................................................................................. 21-83
Split Transactions..................................................................................................... 21-84
Port Test Modes ......................................................................................................21-111
Interrupts................................................................................................................ 21-112
Endpoint Queue Head............................................................................................ 21-117
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Buffer Pointer List Use for Data Streaming with qTDs ...................................... 21-80
Adding Interrupt Queue Heads to the Periodic Schedule.................................... 21-82
Managing Transfer Complete Interrupts from Queue Heads .............................. 21-82
Split Transactions for Asynchronous Transfers................................................... 21-84
Split Transaction Interrupt ................................................................................... 21-86
Split Transaction Isochronous ............................................................................. 21-98
Transfer/Transaction Based Interrupts............................................................... 21-113
Host Controller Event Interrupts ....................................................................... 21-115
Asynchronous—Do-Start-Split........................................................................ 21-85
Asynchronous—Do-Complete-Split ............................................................... 21-85
Split Transaction Scheduling Mechanisms for Interrupt ................................. 21-86
Host Controller Operational Model for FSTNs ............................................... 21-89
Software Operational Model for FSTNs ......................................................... 21-91
Tracking Split Transaction Progress for Interrupt Transfers ........................... 21-92
Split Transaction Execution State Machine for Interrupt ................................ 21-92
Periodic Interrupt—Do-Start-Split .................................................................. 21-93
Periodic Interrupt—Do-Complete-Split .......................................................... 21-94
Managing the QH[FrameTag] Field ................................................................ 21-97
Rebalancing the Periodic Schedule ................................................................. 21-98
Split Transaction Scheduling Mechanisms for Isochronous ........................... 21-99
Tracking Split Transaction Progress for Isochronous Transfers.................... 21-102
Split Transaction Execution State Machine for Isochronous......................... 21-104
Periodic Isochronous—Do-Start-Split........................................................... 21-104
Periodic Isochronous—Do Complete Split ................................................... 21-106
Complete-Split for Scheduling Boundary Cases 2a, 2b ................................ 21-109
Split Transaction for Isochronous—Processing Example ............................. 21-110
Transaction Error ........................................................................................... 21-113
Serial Bus Babble .......................................................................................... 21-113
Data Buffer Error ........................................................................................... 21-114
USB Interrupt (Interrupt on Completion (IOC)) ........................................... 21-115
Short Packet ................................................................................................... 21-115
Port Change Events ....................................................................................... 21-115
Frame List Rollover....................................................................................... 21-115
Interrupt on Async Advance.......................................................................... 21-115
Host System Error ......................................................................................... 21-116
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