MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 490

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 3.0
Table 10-23
10-60
61–62
Bits
60
63
XCBC-MAC and
Finalize Mac for
GCM GHASH
CMAC modes
AUX0 =
AUX0 =
Name
shows the AESU field settings corresponding to different AES cipher modes.
AUX0
Only
CM
ED
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 10-22. AESU Mode Register Field Descriptions (continued)
AUX0 Mode. Definition depends upon the value of the 4 Cipher Mode and Extended Cipher Mode
bits, and Encrypt/Decrypt bit:
Cipher Mode. Used in combination with bits 56:57 (Extended Cipher Mode) to select the cipher
mode for AES operation. See
Encrypt/Decrypt. If set, AESU operates the encryption algorithm; if cleared, AESU operates the
decryption algorithm.
0 Perform decryption
1 Perform encryption
Note: This bit is ignored in CTR, SRT, CMAC, and XCBC-MAC cipher modes.
• GCM Cipher Mode (ECM=10, CM=01) and Encrypt (ED=1): Specifies GHASH mode—performs
• XCBC-MAC, CMAC Cipher Modes (ECM=10, 01, CM=10): Do Not Generate Final MAC
XCBC-MAC with ICV
GHASH on AAD and ciphertext
Bit—Does not generate final MAC tag at the end of message processing (used only when
splitting a message into multiple descriptors)
CMAC with ICV
Cipher Mode
XCBC-MAC
CBC-RBP
LRWXTS
CFB128
0 = Perform GCM encryption
1 = Compute GHASH(H, AAD, ciphertext)
0 = Generate final MAC tag by XORing the final data block with K2/K3 (for XCBC-MAC) or
1 = Do not generate final MAC tag by XORing final data block before encryption. This
CMAC
SRT
CCM
GCM
CBC
ECB
OFB
CTR
1
K1/K2 (for CMAC) before encryption
enables message processing to be interrupted on the block boundary and later
continued after a context switch.
Table 10-23. AES Cipher Modes
ECM (56:57)
Table 10-23
00
00
00
00
00
01
01
01
01
10
10
10
10
10
for mode bit combinations.
Description
AUX2 (58)
X
X
X
X
X
X
X
X
X
X
1
1
0
1
CM (61:62)
00
01
01
10
11
01
10
10
11
00
01
10
10
11
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