MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 701

Manufacturer Part Number

BOARD DEV SYSTEM MPC8536E

Manufacturer

Freescale Semiconductor

PowerQUICC III™r

Board, Software and Documentation

Processor Series

Data Bus Width

Maximum Clock Frequency

Operating Supply Voltage

- 0.3 V to + 1.21 V

Maximum Operating Temperature

Data Ram Size

Interface Type

Program Memory Type

DDR2, DDR3, SDRAM

Program Memory Size

Digital Ic Case Style

Supply Voltage Range

0.95V To 1.05V

Rohs Compliant

For Use With/related Products

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

The FCM provides a glueless interface to parallel-bus NAND Flash EEPROM devices. The FCM contains

three basic configuration register groups—BRn, ORn, and FMR.

Figure 13-46

in FCM mode. Commands, address bytes, and data are all transferred on LAD[0:7]

for transfers written to the device, or LFRE asserted for transfers read from the device. eLBC signals

LFCLE and LFALE determine whether writes are of type command (only LFCLE asserted), address (only

LFALE asserted), or write data (neither LFCLE nor LFALE asserted). The NAND Flash RDY/BSY pin is

normally open-drain, and should be pulled high by a 4.7-K resistor. On system reset, a global (boot)

chip-select is available that provides a boot ROM chip-select (LCS0) prior to the system being fully

1. Note bit numbering reversal: LAD[0] (msb) connects to Flash IO[7], while LAD[7] (lsb) connects to IO[0].

Freescale Semiconductor

Flash Control Machine (FCM)

shows a simple connection between an 8-bit port size NAND Flash EEPROM and the eLBC

Table 13-34. Boot Bank Field Values after Reset for GPCM as Boot Controller

MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1

0000_0000_0000_0000_0

From cfg_rom_loc

Enhanced Local Bus Controller

, with LFWE asserted