MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1009

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x300
Reset
Reset
Table 15-21
15.3.1.14
The DMA general status register combines all of the status bits from each channel into one register. This
register is read-only.
Table 15-22
Freescale Semiconductor
20–31
8–19
Bits
Bits
0–7
W
W
0
1
2
3
4
5
6
7
8
9
R TE0
R TE2
16
0
Name
DSS
DSD
EOLNI0
EOLSI0
EOSI0
Name
—
CH0
CB0
TE0
PE0
TE1
—
—
—
—
17
1
describes the fields of the DSRn.
describes the fields of the DGSR.
DMA General Status Register (DGSR)
Reserved
Destination stride size. Number of bytes to transfer before jumping to the next address as specified in the
destination stride distance field.
Destination stride distance. The destination stride distance in bytes from start byte to start byte.
CH0 PE0
CH2 PE2
18
2
Transfer error, channel 0
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
Channel halted, channel 0
Programming error, channel 0
End-of-links interrupt, channel 0
Channel busy, channel 0
End-of-segment interrupt, channel 0
End-of-lists/direct interrupt, channel 0
Transfer error, channel 1
0 Normal operation
1 An error condition occurred during the DMA transfer.
Reserved
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Figure 15-22
19
3
EOLNI0
EOLNI2
Figure 15-22. DMA General Status Register (DGSR)
20
4
Table 15-22. DGSR Field Descriptions
Table 15-21. DSR n Field Descriptions
describes the DGSR.
CB0
CB2
21
5
EOSI0
EOSI2
22
6
EOLSI0
EOLSI2
All zeros
All zeros
23
7
Description
Description
TE1
TE3
24
8
—
—
25
9
CH1 PE1 EOLNI1 CB1 EOSI1 EOLSI1
CH3 PE3 EOLNI3 CB3 EOSI3 EOLSI3
10
26
11
27
12
28
13
29
Access: Read only
DMA Controller
14
30
15-23
15
31