MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 705

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

software. However, for commands given a specific byte count in FBCR[BC], FPAR[MS] locates the
starting address in either the main region (MS = 0) or the spare region (MS = 1). Where different eLBC
banks control both small and large-page devices, a large-page 4 Kbyte buffer must be assigned to either
the first 4 or last 4 small-page buffers.
13.4.3.1.3
The FCM’s ECC engine makes use of data in the NAND Flash spare region to store pre-computed ECC
code words. ECC is calculated in a single pass over blocks of 512 bytes of data in the main region. The
setting of FMR[ECCM] determines the location of the 24-bit ECC in the spare region.
The basic ECC algorithm is depicted in
matrix having 8 columns (corresponding with the device bus IO[7:0] or IO[15:8]) and 512 rows
(corresponding with each byte in the ECC block). Six bits of parity, {P
calculated across the columns, and at most 18 bits of parity {P
calculated across the rows to create a 24-bit Hamming code for the data block. In this calculation, parity
bit P
N-bit group 0, then continuing to group 2, 4, etc.), while parity bit P
N-bit group of bits positioned at odd intervals (starting at N-bit group 1, then continuing to group 3, 5, etc.).
Freescale Semiconductor
Bank Base Address
N
Figure 13-49. FCM Buffer RAM Memory Map for Large-Page (2-Kbyte page) NAND Flash Devices
’ is the exclusive-OR of every alternate N-bit group of bits positioned at even intervals (starting at
offset 0x1000
offset 0x2000
End of Bank
Error Correcting Codes and the Spare Region
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
buffer #0/page 0
buffer #1/page 1
replicated FCM
buffer RAM
images in bank
Figure
13-50. The stream of data bytes is considered to form a
4 Kbyte page buffer:
2048
N
, P
is the exclusive-OR of every alternate
2048
2048-byte main region (FPAR[MS] = 0)
64-byte spare region (FPAR[MS] = 1)
1984-byte reserved region (FPAR[MS] = 1)
4
, P
’, ..., P
4
’, P
2
16
, P
Enhanced Local Bus Controller
, P
2
’, P
16
’, P
1
, P
8
1
, P
’}, are
8
’} are
13-63