MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 606

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

I
11.4.1.5.1
The different conditions of the I
11.4.1.5.2
The I
of the I
The SDA output can only change at the midpoint of a low cycle of the SCL, unless it is performing a
START, STOP, or restart condition. Otherwise, the SDA output is held constant.
The SDA signal is pulled low when one or more of the following conditions are true in either master or
slave mode:
The SCL signal corresponds to the internal SCL signal when one or more of the following conditions are
true in either master or slave mode:
11-14
2
C Interfaces
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2
C module contains logic that controls the output to the serial data (SDA) and serial clock (SCL) lines
2
START conditions are detected when an SDA fall occurs while SCL is high.
STOP conditions are detected when an SDA rise occurs while SCL is high.
Data transfers in progress are canceled when a STOP condition is detected or if there is a slave address
mismatch. Cancellation of data transactions resets the clock module.
The bus is detected to be busy upon the detection of a START condition, and idle upon the detection
of a STOP condition.
Master mode
— Data bit (transmit)
— Ack bit (receive)
— START condition
— STOP condition
— Restart condition
Slave mode
— Acknowledging address match
— Data bit (transmit)
— Ack bit (receive)
Master mode
— Bus owner
— Lost arbitration
— START condition
— STOP condition
— Restart condition begin
— Restart condition end
Slave mode
— Address cycle
— Transmit cycle
C. The SCL output is pulled low as determined by the internal clock generated in the clock module.
Transaction Monitoring—Implementation Details
Control Transfer—Implementation Details
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
2
C data transfers are monitored as follows:
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