MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1040

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
16.3.1.1
The PCI configuration header, shown in
method utilizing a pair of 32-bit memory-mapped access registers. For PCI, CFG_ADDR is at offset 0x000
and CFG_DATA is at offset 0x004.
16.3.1.1.1
The CFG_ADDR register is shown in
Table 16-4
Bus number 0xb00 and device number 0b0_0000 are used to configure the internal PCI configuration
header of the PCI controller itself.
See
Accessing the PCI Configuration Space,”
16-14
0xE28–
0xF00–
0xEFC
Offset
0xFFC
Offset 0x000
Reset
Section 16.4.2.11.2, “Host Accessing the PCI Configuration Space,”
W
R
EN
0
16–20 Device Number
21–23 Function Number
24–29 Register Number
30–31 —
8–15
Bits
1–7
Reserved
Reserved for debug
describes the bit settings for the CFG_ADDR register.
0
1
PCI Configuration Access Registers
PCI Configuration Address Register (CFG_ADDR)
Bus Number
Enable
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
Name
Table 16-3. PCI Memory-Mapped Register Map (continued)
7
Table 16-4. PCI CFG_ADDR Field Descriptions
8
Figure 16-3. PCI CFG_ADDR Register
Register
Allow a PCI configuration access when PCI CFG_DATA is accessed
Reserved
PCI bus number to access
Device number to access on specified bus
Function to access within specified device
32-bit register to access within specified device
Reserved, hardwired to logic 00
Bus Number
Figure
Figure 16-24
for usage of PCI CFG_ADDR.
16-3.
All zeros
15 16
and
Device Number
Figure
Description
16-58, is accessed through an indirect
20 21
Access
Function
Number
—
—
and
23 24
Section 16.4.2.11.3, “Agent
Reset
Register Number
—
—
Freescale Semiconductor
Access: Read/Write
Section/page
29 30 31
—