MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1100

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Express Interface Controller
17.1.3
Several parameters that affect the PCI Express controller modes of operation are determined at power-on
reset (POR) by reset configuration signals as described in
17.1.3.1
The PCI Express controller can function as either a root complex (RC) or an endpoint (EP) on the PCI
Express link. The host/agent configuration input signals cfg_host_agt[0:2] determine the RC/EP mode.
17.1.3.2
The MPC8536E initial link widths are determined by POR configuration signals as described in
Section 17.1.3, “Modes of
527 MHz or greater.
17.2
PCI Express defines the connection between two devices as a link, which can be composed of a single or
multiple lanes. Each lane consists of a differential pair for transmitting (TXn and TXn) and a differential
pair for receiving (RXn and RXn) with an embedded data clock.
Although the generic PCI Express controller described here accommodates up to a single 8 link, there are
three PCI Express controllers instantiated on the MPC8536E. Please refer to
17-4
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Host/Agent Configuration Selects between root complex (RC) and endpoint (EP) modes.
Baseline and advanced error reporting support
One virtual channel (VC0)
256-byte maximum payload size (MAX_PAYLOAD_SIZE)
Supports three inbound general-purpose translation windows and one configuration window
Supports four outbound translation windows and one default window
Supports eight non-posted and four posted PCI Express transactions
Supports up to six priority 0 internal platform reads and eight priority 0 to 2 internal platform
writes. (The maximum number of outstanding transactions at any given time is eight.)
Credit-based flow control management
Supports PCI Express messages and interrupts
Accepts up to 256-byte transactions from the internal platform (OCeaN)
I/O Port Selection
External Signal Descriptions
Modes of Operation
Parameter
Root Complex/Endpoint Modes
Link Width
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-1. POR Parameters for PCI Express Controller
Operation.” Note that the x8 link width is only available at CCB clock rates of
Selects the width of the PCI Express links
Description
Chapter 4, “Reset, Clocking, and Initialization.”
Section 4.4.3.8, “SerDes1 I/O
Freescale Semiconductor
Section/Page
4.4.3.7/4-15
4.4.3.8/4-16