MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 501

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Context for SRT Cipher Mode
As mentioned in the footnote to
method of performing AES-CTR cipher mode with reduced context loading overhead specifically for
performing SRTP. As with CTR cipher mode, a random 128-bit initial counter value is incremented
modulo 2
derive the ciphertext, or with the ciphertext to recover the plaintext. The modulus exponent M can be set
between 8 and 128 in multiples of 8.
As shown in
register 3 holds the modulus exponent M .
10.7.1.11.2 Context for Data Integrity Cipher Modes
The context registers for the different cipher modes which provide data integrity only are summarized in
Table
Freescale Semiconductor
5. Set Key size
6. Set Data size
7. While available:
8. Write to the end of message register
9. Unload final ciphertext (for encryption) or plaintext (for decryption) blocks
10-30. The registers are described in more detail in the following subsections.
little-endian format.
a.
b. Unload ciphertext (for encryption) or plaintext (for decryption) blocks
M
with each block processed. The running counter is encrypted and XORed with the plaintext to
Load plaintext (for encryption) or ciphertext (for decryption) blocks
Table
Context Register #
10-29, in SRT mode context registers 1–2 hold the initial counter value, and context
(byte address)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
10 (0x34148)
1 (0x34100)
2 (0x34108)
3 (0x34110)
4 (0x34118)
5 (0x34120)
6 (0x34128)
7 (0x34130)
8 (0x34138)
9 (0x34140)
Table 10-30. AESU Context Registers for Integrity Modes
Table
Computed MAC
Received MAC*
10-23, SRT is not a new AES cipher mode but rather an AESU
XCBC-MAC
Key 1
Key 2
Key 3
Cipher Mode providing only Data Integrity
Computed MAC
GCM-GHASH
len(AAD)
H
T
CMAC (OMAC1)
Computed MAC
Received MAC*
E(K, 0
128
)
Security Engine (SEC) 3.0
10-71