MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 267

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

7.2.1.3
The ECM IP block revision register 1 is shown in
Table 7-4
7.2.1.4
The ECM IP block revision register 2 is shown in
Freescale Semiconductor
Offset 0x0_1BF8
Reset 0
30–31
Bits
29
W
16–23
24–31
R
0–15
Bits
0
CPU_RD_HI_DIS Identifies which read queue of DDR targets is assigned to the e500 core (CPU) port’s read
Offset 0x0_1BFC
Reset
0
describes EIPBRR1 fields.
CPU_PRI
W
R
Name
0
IP_MN
IP_MJ
Name
IP_ID
0
ECM IP Block Revision Register 1 (EIPBRR1)
ECM IP Block Revision Register 2 (EIPBRR2)
0
0
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
IP block ID
Major revision
Minor revision
0
—
transactions (in understressed system).
0
1
Specifies the priority level of the e500 core 0 (CPU) port. This priority level is used to determine
whether a particular port’s bus request can cause the CCB arbiter to terminate another port’s
streaming of address tenures.
00 Lowest priority level
01 Second lowest priority level
10 Highest priority level
11 Reserved
Figure 7-4. ECM IP Block Revision Register 1 (EIPBRR1)
Figure 7-5. ECM IP Block Revision Register 2 (EIPBRR2)
0
Read high queue (higher bandwidth DDR queue) is assigned for the e500 core’s read
transactions
Read low queue (lower bandwidth DDR queue) is assigned for the e500 core’s read
transactions
Table 7-3. EEBPCR Field Descriptions (continued)
IP_ID
0
0
7
Table 7-4. EIPBRR1 Field Descriptions
0
8
0
0
IP_INT
0
0
Figure
0
Figure
15 16
All zeros
1
15 16
0
Description
7-4.
7-5.
Description
0
0
IP_MJ
0
—
0
0
0
23 24
23 24
0
0
Access: Read only
0
IP_CFG
e500 Coherency Module
0
Access: Read only
IP_MN
0
0
0
31
0
7-5
31
0