MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1080

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PCI Bus Interface
As a target, the PCI controller responds to a transaction with a retry due to the following:
Target-abort is indicated by asserting PCI_STOP and negating PCI_DEVSEL. This indicates that the
target requires termination of the transaction and does not want the transaction retried. If a transaction is
terminated by target-abort, the received target-abort bit (bit 12) of the initiator’s bus status register and the
signaled target-abort bit (bit 11) of the target’s bus status register are set. Note that any data transferred in
a target-aborted transaction may be corrupt.
For PCI writes to local memory, if an address parity error or data parity error occurs, the PCI controller
aborts the transaction internally, but continues the transaction on the PCI bus.
16-54
•
•
•
•
•
•
It is unable to respond within eight PCI clock cycles (not including the first data phase).
The transaction is attempting to cross a 4-Kbyte boundary.
A single beat of data has been transferred and the inbound ATMU is marked non-prefetchable.
The end of a cache line has been transferred for a cache-wrap mode write transaction. See
Section 16.4.2.3.1, “Memory Space Addressing,”
The
There is no more internal buffer space available for an inbound transaction.
32-clock
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
latency timer has expired, and the first data phase has not begun.
for more information.
Freescale Semiconductor