MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1353

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.3.2.7
This register is not defined in the EHCI specification. In device mode, the upper seven bits of this register
represent the device address. After any controller reset or a USB reset, the device address is set to the
default address (0). The default address will match all incoming addresses. Software shall reprogram the
address after receiving a SET_ADDRESS descriptor.
Note that this register is shared between the host and device mode functions. In device mode, it is the
DEVICEADDR register; in host mode, it is the PERIODICLISTBASE register. See
“Periodic Frame List Base Address Register (PERIODICLISTBASE),”
21.3.2.8
This 32-bit register contains the address of the next asynchronous queue head to be executed by the host.
Bits 4–0 of this register cannot be modified by the system software and always return zeros when read.
Note that this register is shared between the host and device mode functions. In host mode, it is the
ASYNCLISTADDR register; in device mode, it is the ENDPOINTLISTADDR register. See
Freescale Semiconductor
31–12
31–25
11–0
24–0
Offset 0x154
Reset n
Offset 0x154
Reset
Bits
Bits
W
W
R
R
31
31
USBADR
PERBASE
Name
Name
n n n n
—
—
Device Address Register (DEVICEADDR)—Non-EHCI
Current Asynchronous List Address Register (ASYNCLISTADDR)
USBADR
Figure 21-12. Periodic Frame List Base Address (PERIODICLISTBASE)
Device address. This field corresponds to the USB device address.
Reserved, should be cleared.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
Base address. Correspond to memory address signal [31:12]. Only used in the host mode.
Table 21-14. PERIODICLISTBASE Register Field Descriptions
n n n n n
Table 21-15. DEVICEADDR Register Field Descriptions
25 24
Figure 21-13. Device Address (DEVICEADDR)
PERBASE
n n n n
n n 0 0 0
All zeros
Description
Description
12 11
0
—
0
0
for more information.
0
0
Universal Serial Bus Interfaces
0
0
Section 21.3.2.6,
—
0
Access: Read/Write
Access: Read/Write
0
0
0
0
21-19
0
0
0