MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1477

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

21.9.1.1
The following additions have been added to the capability registers to support the embedded transaction
translator Function:
See
21.9.1.2
The following additions have been added to the operational registers to support the embedded TT:
21.9.1.3
In a standard EHCI controller design, the EHCI host controller driver detects a Full speed (FS) or Low
speed (LS) device by noting if the port enable bit is set after the port reset operation. The port enable will
only be set in a standard EHCI controller implementation after the port reset operation and when the host
and device negotiate a High-Speed connection (that is, Chirp completes successfully).
The module will always set the port enable after the port reset operation regardless of the result of the host
device chirp result and the resulting port speed will be indicated by the PSPD field in PORTSC. Therefore,
the standard EHCI host controller driver requires an alteration to handle directly connected Full and Low
speed devices or hubs. The change is a fundamental one in that is summarized in
21.9.1.4
The same data structures used for FS/LS transactions though a HS hub are also used for transactions
through the Root Hub. Here it is demonstrated how the Hub Address and Endpoint Speed fields should be
set for directly attached FS/LS devices and hubs:
Freescale Semiconductor
After port enable bit is set following a connection and
reset sequence, the device/hub is assumed to be HS.
FS and LS devices are assumed to be downstream
from a HS hub thus, all port-level control is performed
through the Hub Class to the nearest Hub.
FS and LS devices are assumed to be downstream
from a HS hub with HubAddr=X. [where HubAddr > 0
and HubAddr is the address of the Hub where the bus
transitions from HS to FS/LS (that is, Split target hub)]
•
•
•
•
1. QH (for direct attach FS/LS)—Async. (Bulk/Control Endpoints) Periodic (Interrupt)
Section 21.3.1.3, “Host Controller Structural Parameters (HCSPARAMS),”
N_TT added to HSCPARAMS - Host Controller Structural Parameters
N_PTT added to HSCPARAMS - Host Controller Structural Parameters
ASYNCTTSTS is a new register.
Addition of two-bit Port Speed (PSPD) to the PORTSC register.
Table 21-95. Functional Differences Between EHCI and EHCI with Embedded TT
Capability Registers
Operational Registers
Discovery
Data Structures
Standard EHCI
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
After port enable bit is set following a connection and reset sequence,
the device/hub speed is noted from PORTSC.
FS and LS device can be either downstream from a HS hub or directly
attached. When the FS/LS device is downstream from a HS hub, then
port-level control is done using the Hub Class through the nearest Hub.
When a FS/LS device is directly attached, then port-level control is
accomplished using PORTSC.
FS and LS device can be either downstream from a HS hub with
HubAddr = X [HubAddr > 0] or directly attached [where HubAddr = 0 and
HubAddr is the address of the Root Hub where the bus transitions from
HS to FS/LS (that is, Split target hub is the root hub)]
EHCI with Embedded Transaction Translator
for usage information.
Universal Serial Bus Interfaces
Table
21-95.
21-143