MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1500

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Global Utilities
23.4.1.3
PORIMPSCR, shown in
interfaces.
The I/O impedance of local bus signals (including the local bus clock) is controlled through this register.
The I/O impedance of PCI signals is controlled by POR configuration pins (described in
“PCI I/O
impedances.
Table 23-6
23-8
13–15
16–31
Offset 0x008
Bits
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
R
0
Impedance”). The MPC8536E Integrated Processor Hardware Specification provides exact I/O
Name
HA
16–24
25–31 LBC_Z I/O impedance for these local bus signals: LAD[0:31], LDP[0:3], LA[27:31], LCS[0:7],
—
describes PORIMPSCR fields.
0–14
Bits
15
POR I/O Impedance Status and Control Register (PORIMPSCR)
Figure 23-3. POR I/O Impedance Status and Control Register (PORIMPSCR)
Host/agent mode configuration. When the MPC8536E is an agent on an interface, it is prevented from
mastering transactions on that interface until the external host configures the interface appropriately.
000 Reserved
001 PCI Express 3 endpoint
010 Reserved
011 PCI Express 2 endpoint
100 Reserved
101 PCI Express 1 endpoint
110 PCI agent mode
111 Host mode/root complex on all interfaces
Reserved
PCI_Z PCI I/O impedance
Name
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
—
Figure
Reserved
0 Low impedance
1 High impedance
Reserved
LWE[0:3], LGP[0:5], LCKE, LCLK
Note: Other signals use a fixed high I/O impedance
11111111 High impedance
else Low impedance
Table 23-5. PORBMSR Field Descriptions (continued)
—
Table 23-6. PORIMPSCR Field Descriptions
23-3, contains the current I/O driver impedances for local bus and PCI
14
0
PCI_Z
15
n
Description
Description
16
0
0 0 0 0 0 0 0
—
24 25
0
Freescale Semiconductor
1 1 1 1 1 1
Section 4.4.3.20,
LBC_Z
Access: Mixed
31
1