MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 467

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.4.3.1.4
The data bytes out counter, shown in
an EU output FIFO. If other parcels such as context or ICV are read from the output FIFO, they are not
counted. In no case is data counted twice by the same counter.
If this counter reaches all 1s, at the next count it rolls over to all 0s and the interrupt enable register’s
DO_CNT bit is set (see
(IER, ISR,
If this counter is read by software in 32-bit increments, then the least significant 32 bits must be read first,
followed by the most significant 32 bits. If this counter is written by software in 32 bit increments, then
the most significant 32 bits must be written first, followed by the least significant 32 bits. Note that 32 bit
reads and writes must not be interleaved (that is, read low, write low, read high, write high is not allowed).
These restrictions are required to maintain counter coherency.
10.4.4
The channel registers are replicated for each of the 4 channels in the polychannel.
10.4.4.1
This register contains bits that allow the user to configure and reset the channel. The CCR fields are shown
in
Freescale Semiconductor
Offset Channel 0x3_1510
Reset
Offset Channel 0x3_1518
Reset
Figure
W
R
W
R
0
0
10-11, and described in
ICR)”).
Channel Registers
Channel Configuration Register (CCR)
Data Bytes Out Counter
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Section 10.5.4.2, “Interrupt Enable, Interrupt Status, and Interrupt Clear Registers
Table
Figure 10-10. Data Bytes Out Counter
Figure 10-9. Data Bytes In Counter
Figure
10-11.
10-10, indicates the total number of payload bytes read from
Data_Bytes_Out_Count
Data_Bytes_In_Count
31 32
All zeros
All zeros
31 32
Security Engine (SEC) 3.0
Access: Read/Write
Access: Read/Write
10-37
63
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