MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 201

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Configuration Words Section
The configuration words section is comprised of Config Address and Config Data pairs of adjacent 32-bit
fields. These are typically used to configure the local access windows and the target memory controller’s
registers. They are therefore system-dependent, as they need to be aware of the type and configuration of
memory in a particular system.
The Config Address field has two modes that are selected by the least significant bit in the field (CNT). If
the CNT bit is clear, then the 30 most significant bits are used to form the address pointer and the Config
Data contains the data to be written to this address. If the CNT bit is set then the 30 most significant bits
are used for control instruction. This flexible structure allows the user to configure any 4-byte aligned
memory mapped register, perform control instructions, and specify the end of the configuration stage.
Note that it is illegal to change the content of the CCSRBAR by using this mechanism. Any attempt to do
so will cause the boot process to hang.
The upper 4 most-significant address bits of the 36-bit address are always zero. Consequently the
configuration words can only access memory in the lowest 4 GByte segment of memory. However, since
by default CCSRBAR maps all memory mapped registers within the lowest 4 GByte segment of memory,
and the user is prohibited from changing CCSRBAR with a configuration access, this is not an issue.
The Config Address structure is shown in
defines the Config Address bits when CNT = 0 (address mode).
Freescale Semiconductor
CNT = 0
CNT = 1 EC DLY
0–29
Bits
30
31
0
1
Address
Name
CNT
—
2
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 4-36. Config Address Field Description, CNT = 0
Address bits 0–29. The data in the Config Data field is copied by the e500 core to this
address. The two least significant bits of the address (30:31) are always considered to be
zero, as are the upper 4 bits of the 36-bit address.
Reserved. Must be zero.
Control. Select between Address mode and Control mode.
0 Address mode
1 Control mode
Figure 4-9. Config Address Fields
Figure
Address
4-12.
—
Description
Reset, Clocking, and Initialization
29 30
— CNT
CNT
31
4-31