MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 537

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0x3_F100
Offset 0x3_F100
Offset 0x3_F100
Offset 0x3_F100
Reset
Reset
Reset 1
Reset 1
Reset 1
If the CRCU is in the default output mode (DOS and DOC bits are 0), this register holds the CRC
remainder after it has been bit swapped, byte swapped, and complemented. This sequence of operations is
described in the protocol specifications and generates a result, which can be written directly to the end of
a frame or command. The result is shown in
If the CRCU is in the disable output swap mode (DOS bit is 1), this register holds the unswapped but
complemented CRC remainder, as shown in
If the CRCU is in the disable output complement mode (DOC bit is 1), this register holds the
uncomplemented but swapped CRC remainder, as shown in
Freescale Semiconductor
W
W
W
W
W
R
R
R
R
R
x
x
x
x
32
0
31
0
24
0
31
0
24
x
x
x
x
1
1
1
1
30
1
25
1
30
1
25
x
x
x
x
2
2
1
2
1
2
1
29
26
29
26
x
x
x
x
1
1
1
3
28
3
27
3
28
3
27
Figure 10-51. CRCU Context Register, Upper Half (Read in Default Mode)
x
x
x
x
Figure 10-52. CRCU Context Register, Upper Half (Read in DOS Mode)
Figure 10-53. CRCU Context Register, Upper Half (Read in DOC Mode)
4
4
1
4
1
4
1
27
28
27
28
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
x
x
x
x
1
1
1
5
5
5
5
26
29
26
29
x
x
x
x
1
1
1
6
25
6
30
6
25
6
30
x
x
x
x
1
1
1
7
24
7
31
7
24
7
31
Figure 10-50. CRCU Context Register (Write)
x
x
x
x
8
8
8
8
23
16
23
16
x
x
x
x
1
1
1
9
9
9
9
22
17
22
17
x
x
x
x
10
10
10
10
1
1
1
21
18
21
18
x
x
x
x
11
11
11
11
1
1
1
20
19
20
19
Figure
Figure
x
x
x
x
12
12
12
12
1
1
1
19
20
19
20
x
x
x
x
13
13
13
13
1
1
1
18
21
18
21
10-52.
All zeros
All zeros
10-51.
x
x
x
x
14
14
14
14
1
1
1
17
22
17
22
—
x
x
x
x
15
15 16 17 18
15
15 16 17 18
1
1
1
16
23
16
23
x
x
x
x
Figure
16
16
15
8
15
8
x
x
1
1
x
9
x
9
17
17
1
14
14
x
x
1
1
10
10
x
x
10-53.
18
18
1
13
13
x
x
19
19
1
1
11
11
x
x
19
19
1
12
12
x
x
20
20
1
1
12
12
x
x
20
20
1
11
11
x
x
21
21
1
1
13
13
x
x
21 22 23 24 25 26 27 28 29 30 31
21 22 23 24 25 26 27 28 29 30 31
1
10
10
x
x
22
22
1
1
14
14
x
x
1 1 1 1 1 1 1 1 1 1
9
9
x
x
23 24 25 26 27 28 29 30 31
23 24 25 26 27 28 29 30 31
1
1
x
x
15
15
Security Engine (SEC) 3.0
8
8
x
x
x
x
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
7
0
7
0
x
x
x
x
6
1
6
1
Access: Read/Write
Access: Read/Write
Access: Read/Write
Access: Read/Write
x
x
x
x
5
2
5
2
x
x
x
x
4
3
4
3
x
x
x
x
3
4
3
4
10-107
x
x
x
x
2
5
2
5
x
x
x
x
1
6
1
6
x
63
x
x
x
0
7
0
7