MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 47

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
21.8.5.6
21.8.6
21.8.6.1
21.8.6.2
21.8.6.3
21.9
21.9.1
21.9.1.1
21.9.1.2
21.9.1.3
21.9.1.4
21.9.1.5
21.9.1.5.1
21.9.1.5.2
21.9.1.5.3
21.9.1.5.4
21.9.1.5.5
21.9.2
21.9.3
21.9.4
21.9.5
21.9.5.1
21.9.6
21.9.6.1
21.9.6.2
21.9.6.2.1
21.9.6.2.2
21.10
22.1
22.1.1
22.1.2
22.2
22.2.1
22.3
22.3.1
22.3.2
22.3.3
Freescale Semiconductor
Deviations from the EHCI Specifications ................................................................. 21-142
Timing Diagrams ....................................................................................................... 21-148
Introduction.................................................................................................................... 22-1
External Signal Description ........................................................................................... 22-2
Memory Map/Register Definition ................................................................................. 22-2
Servicing Interrupts................................................................................................ 21-141
Embedded Transaction Translator Function .......................................................... 21-142
Device Operation ................................................................................................... 21-146
Non-Zero Fields the Register File ......................................................................... 21-146
SOF Interrupt ......................................................................................................... 21-146
Embedded Design .................................................................................................. 21-146
Miscellaneous Variations from EHCI .................................................................... 21-147
Overview.................................................................................................................... 22-1
Features...................................................................................................................... 22-1
Signals Overview....................................................................................................... 22-2
GPIO Direction Register (GPDIR) ............................................................................ 22-2
GPIO Open Drain Register (GPODR)....................................................................... 22-3
GPIO Data Register (GPDAT)................................................................................... 22-3
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Device Error Matrix........................................................................................... 21-140
High-Frequency Interrupts................................................................................. 21-141
Low-Frequency Interrupts ................................................................................. 21-141
Error Interrupts .................................................................................................. 21-142
Capability Registers........................................................................................... 21-143
Operational Registers......................................................................................... 21-143
Discovery ........................................................................................................... 21-143
Data Structures................................................................................................... 21-143
Operational Model ............................................................................................. 21-144
Frame Adjust Register ....................................................................................... 21-147
Programmable Physical Interface Behavior ...................................................... 21-147
Discovery ........................................................................................................... 21-147
Microframe Pipeline ...................................................................................... 21-144
Split State Machines ...................................................................................... 21-145
Asynchronous Transaction Scheduling and Buffer Management ................. 21-145
Periodic Transaction Scheduling and Buffer Management ........................... 21-145
Multiple Transaction Translators................................................................... 21-146
Port Reset....................................................................................................... 21-147
Port Speed Detection ..................................................................................... 21-147
General Purpose I/O (GPIO)
Contents
Chapter 22
Title
Number
Page
xlvii