MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 789

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 14-16
Freescale Semiconductor
21–26
0–16
Bits
17
18
19
20
27
28
RFC_PAUSE Receive flow control pause frame (written by the eTSEC). This read-only status bit is set if a flow control
TFC_PAUSE Transmit flow control pause frame. Set this bit to transmit a PAUSE frame. If this bit is set, the MAC stops
TUCSEN
IPCSEN
VLINS
Name
THDF
—
—
describes the fields of the TCTRL register.
Reserved
IP header checksum generation enable. When set, the eTSEC offloads IPv4 header checksum
generation. See
0 IP header checksum generation is disabled even if enabled in a transmit frame control block.
1 IP header checksum generation is performed for IPv4 headers as determined by the settings in the
TCP/UDP header checksum generation enable. When set, the eTSEC offloads TCP or UDP header
checksum generation. See
page
0 TCP or UDP header checksum generation is disabled even if enabled in a transmit frame control block.
1 TCP or UDP header checksum generation is performed as determined by the settings in the current
VLAN (IEEE Std. 802.1Q) tag insertion enable. Applicable only for transmission through the Ethernet
MAC.
0 Do not insert a VLAN tag into the frame.
1 Insert a VLAN tag into the frame. If the frame FCB has a valid VLAN field, use the FCB to source the
Transmit half-duplex flow control under software control for 10-/100-Mbps half-duplex media. This bit is
not self-resetting.
0 Disable back pressure
1 Back pressure is applied to media by raising carrier
Reserved
pause frame was received and the transmitter is paused for the duration defined in the received pause
frame. This bit automatically clears after the pause duration is complete.
0 Pause duration complete.
1 Flow control pause frame received.
transmission of data frames after the currently transmitting frame completes. Next, the MAC transmits a
pause control frame with the duration value obtained from the PTV register. The TXC event occurs after
sending the pause control frame. Finally, the controller clears TFC_PAUSE and resumes transmitting
data frames as before. Note that pause control frames can still be transmitted if the Tx controller is
stopped due to user assertion of DMACTRL[GTS] or reception of a PAUSE frame.
0 No request for Tx PAUSE frame pending or transmission complete.
1 Software request for Tx PAUSE frame pending.
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
current transmit frame control block.
transmit frame control block.
VLAN control word, otherwise take the default VLAN control word from register DFVLAN.
14-178.
Section 14.6.4.2, “Transmit Path Off-Load and Tx PTP Packet Parsing,” on page
Table 14-16. TCTRL Field Descriptions
Section 14.6.4.2, “Transmit Path Off-Load and Tx PTP Packet Parsing,” on
Description
Enhanced Three-Speed Ethernet Controllers
14-178.
14-41