MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 331

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.4.1.39
The memory error interrupt enable register, shown in
select error interrupts. When an enabled interrupt condition occurs, the internal int signal is asserted to the
programmable interrupt controller (PIC).
Table 8-45
Freescale Semiconductor
Offset 0xE48
Reset
25–27
0–22
Bits
23
24
28
29
30
31
W
R
0
MBEE Multiple-bit ECC error interrupt enable. Note that uncorrectable read errors may cause the assertion of
MSEE Memory select error interrupt enable
Name
APEE Address parity error interrupt enable
ACEE Automatic calibration error interrupt enable
SBEE Single-bit ECC error interrupt enable
—
—
—
describes the ERR_INT_EN fields.
Memory Error Interrupt Enable (ERR_INT_EN)
Reserved
0 Address parity errors cannot generate interrupts.
1 Address parity errors generate interrupts.
0 Automatic calibration errors cannot generate interrupts.
1 Automatic calibration errors generate interrupts.
Reserved
core_fault_in , which causes the core to generate a machine check interrupt, unless it is disabled (by clearing
HID1[RFXE]). If RFXE is zero and this error occurs, MBEE and ERR_DISABLE[MBED] must be zero and
DDR_SDRAM_CFG[ECC_EN] must be set to ensure that an interrupt is generated. For more information, see
Section 5.2, “e500 Core Integration and the Core Complex Bus
Reference Manual .
0 Multiple-bit ECC errors cannot generate interrupts.
1 Multiple-bit ECC errors generate interrupts.
0 Single-bit ECC errors cannot generate interrupts.
1 Single-bit ECC errors generate interrupts.
Reserved
0 Memory select errors do not cause interrupts.
1 Memory select errors generate interrupts.
Figure 8-40. Memory Error Interrupt Enable Register (ERR_INT_EN)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 8-45. ERR_INT_EN Field Descriptions
—
All zeros
Figure
Description
8-40, enables ECC interrupts or memory
22
APEE ACEE
23
(CCB),” and the PowerPC™ e500 Core Family
24
25
—
27
MBEE SBEE — MSEE
28
DDR Memory Controller
Access: Read/Write
29
30
31
8-57