MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 946

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
Figure 14-152
14-198
Second TxBD[Data Buffer Pointers] points to start of L2 or frame data If there is only one TxBD used to transfer a PTP
The TxFCB is followed immediately by a minimum of 16 bytes for the
Second TxBD[Data Length] >= FIFO_TX_THR or includes the entire
TX BD Ring
First TxBD[Data Buffer Pointer] is 8-byte aligned
First TxBD[Data Length]=8, 8 bytes for TxFCB
depicts the buffer format requirements for time-stamp insertion on transmit packets.
Data Buffer Length=8
Data Buffer Pointer
Data Buffer Length=M
Data Buffer Pointer
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 14-167. Time-Stamp Insertion Programming Requirements
Figure 14-152. Buffer Format for Transmit Time-Stamp Insertion
TxFCB[PTP]=1
TxBD[TOE]=1
Requirement
TxPAL
frame
TOE=1
External Memory
the time-stamp may be invalid, and the Second
If L2 or frame data is included in the Length, the
time-stamp value after the frame is transmitted.
frame, then no time-stamp is written to a TxPAL.
If TxBD[TOE]=0, then no time-stamp is written
The time-stamp will be written to address First
If TxBD[PTP]=0, then no time-stamp is written
The time-stamp will be written to address First
except at 4K page boundaries, in which case
If this condition is not true, the time-stamp in
down to the nearest 8-byte aligned address,
stored in memory will be overwritten with a
TxBD[Data Buffer Pointer] + 0x10 rounded
transmitted on the line and the frame data
0 1
32B cache-lines
buffer immediately following the FCB is
Behavior if requirement is not met
TxBD[Data Buffer Pointer] + 0x10.
FCB
TxBD close status will be lost.
8 Bytes
2
TxPAL is invalid.
3
to a TxPAL.
to a TxPAL.
...
Freescale Semiconductor
7
TxPAL
TxPAL
TxFCB
TxPAL
FRAME
Unknown
Unknown