MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 919

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If flow-control mode is enabled (MACCFG1[Rx_Flow] is set) and the receiver identifies a pause-flow
control frame, transmission stops for the time specified in the control frame. The controller completes any
frame in progress before stopping transmission and does not commence counting the pause time until
transmit is idle. During a pause, only a control frame can be sent (TCTRL[TFC_PAUSE] is set). Normal
transmission resumes after the pause timer stops counting, or resumes immediately if a pause frame with
a zero time-out is received. If another pause-control frame is received during the pause, the period changes
to the new value received.
14.6.3.10 Interrupt Handling
Freescale Semiconductor
The following describes what usually occurs within a eTSEC interrupt handler:
•
•
•
Size [Octets]
If an interrupt occurs, read IEVENT to determine interrupt sources. IEVENT bits to be handled in
this interrupt handler are normally cleared at this time. There are three kinds of interrupts:
— Receive data frame interrupts, when bits RXB or RXF in IEVENT are set
— Transmit data frame interrupts, when bits TXB or TXF in IEVENT are set
— Error, diagnostic, and special interrupts (all bits in IEVENT other than RXB, RXF, TXB, or
Process the TxBDs to reuse them if the IEVENT[TXB, TXF or TXE] were set. Consult register
bits TSTAT[TXF0–TXF7] to determine which TxBD rings gave rise to the transmit interrupt in the
case of TXF. If the transmit speed is fast or the interrupt delay is long, more than one transmit buffer
may have been sent by the eTSEC; thus, it is important to check more than just one TxBD during
the interrupt handler. One common practice is to process all TxBDs in the interrupt handler until
one is found with R set.
Obtain data from RxBD rings if IEVENT[RXC, RXB or RXF] is set. Consult register bits
RSTAT[RXF0–RXF7] to determine which RxBD rings gave rise to the receive interrupt in the case
of RXF. If the receive speed is fast or the interrupt delay is long, the eTSEC may have received
more than one RxBD; thus, it is important to check more than just one RxBD during interrupt
handling. Typically, all RxBDs in the interrupt handler are processed until one is found with E set.
Because the eTSEC pre-fetches BDs, the BD table must be big enough so that there is always
another empty BD to pre-fetch, otherwise a BSY error occurs.
40
2
2
2
4
TXF)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
MAC parameter
Extended MAC
MAC opcode
Description
parameter
Reserved
Table 14-152. Flow Control Frame Structure (continued)
FCS
Value
00-01
—
Pause command
Pause time as defined by the PTV[PT] field. The pause
period is measured in pause_quanta, a speed
independent constant of 512 bit-times (unlike slot time).
The most-significant octet is transmitted first.
Pause time extended as defined by the PTV[PTE] field.
The most significant octet is transmitted first.
Frame check sequence (CRC)
Enhanced Three-Speed Ethernet Controllers
Comment
—
14-171