MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 934

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
14.6.5.2.3
It is frequently useful to create rules that are guaranteed to succeed or fail, specifically to enforce a default
filing decision or act as null entries. Suggested constructions for such rules are shown in
14.6.5.2.4
The filer can produce three interrupt events in IEVENT. Event FIR indicates an error condition where the
filer was unable to provide a definite result, either because no rule in the table succeeded, or because
frames arrived too rapidly to complete searching of the table. Event FIQ indicates that the filer accepted a
frame to a RxBD ring that was not enabled in RQCTRL (this can also occur if the filer is disabled, but
RxBD ring 0—default queue or FSQEN mode queue—is not enabled). FIQ is also asserted in the case
where no rule in the entire table succeeded. The various combinations of these interrupt events and their
interpretation appear in
A functional interrupt is provided via use of the general purpose interrupt (GPI) bit in the filer table. When
a property matches the value in the RQPROP entry at this index, and REJ = 0 and AND = 0, the filer will
set IEVENT[FGPI] when the corresponding receive frame is written to memory. This allows the user to
set up a filer rule where the core will be interrupted upon the reception of ‘special’ frames.
If the timer is enabled (TMR_CTRL[TE] = 1), then the interrupt dedicated for timer events (in addition to
the usual receive, transmit and error interrupts) will be asserted.
14-186
IEVENT[FIR] IEVENT[FIQ]
1
2
3
Default file—Always file frame to ring Q
Default reject—Always discard frame
Empty rule in AND—Always matches
Empty rule in rule set—Always fails
Hexadecimal digits qq denotes field Q shifted left 2 bits.
Set CLE = 1 if the empty rule guards a cluster.
Set CLE = 1 if the empty rule occurs at the end of a cluster.
0
0
1
1
Rule Description
Special-Case Rules
Filer Interrupt Events
0
1
0
1
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table
No error. The filer successfully rejected or filed a frame.
Illegal queue error. The filer accepted a frame to a RxBD ring that is disabled (including ring 0 if
filing is disabled).
Partial search error. The filer did not have sufficient time to complete its search of the filer table.
No matching rule error. The filer searched all 256 entries of the filer table without finding a rule
that succeeds.
Table 14-162. Receive Queue Filer Interrupt Events
14-162.
Table 14-161. Special Filer Rules
CLE REJ AND
0/1
0/1
0
0
2
3
0
1
0
0
0
0
1
0
RQCTRL Fields
000_000
000_000
000_000
Q
Q
Description
CMP
01
01
01
11
0000
0000
0000
0000
PID
0xFFFF_FFFF
0xFFFF_FFFF
0x0000_0000
0x0000_0000
RQPROP
Word
Freescale Semiconductor
Table
0x0000_00A0
0x0000_ qq 20
0x0000_0120
0x0000_0060
RQCTRL
Word
14-161.
1