MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1130

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Offset 0xE10
Reset
Reset
PCI Express Interface Controller
17.3.6.3
The PCI Express error disable register, shown in
detect register’s bits.
Table 17-25
17-34
24–31
W
W
Bits
R
R
21
22
23
CRSTD MISD IOISD CISD CIEPD IOIEPD OACD IOIAD
Bits
1–7
10
MED
0
8
9
16
0
IOIEPIE
OACIE
IOIAIE
Name
Table 17-24. PCI Express Error Interrupt Enable Register Field Descriptions (continued)
—
PCACD
Name
PCTD
17
MED
1
describes the fields of the PCI Express error disable register.
PCI Express Error Disable Register (PEX_ERR_DISR)
—
—
I/O invalid EP interrupt enable. When set and PEX_ERR_DR[IOIEP]=1 generates an interrupt.
1 Enable outbound I/O transaction EP mode interrupt generation
0 Disable outbound I/O transaction EP mode interrupt generation
Outbound ATMU crossing interrupt enable. When set and PEX_ERR_DR[OAC]=1 generates an interrupt.
1 Enable outbound crossing ATMU interrupt generation
0 Disable outbound crossing ATMU interrupt generation
I/O address invalid enable. When set and PEX_ERR_DR[IOIA]=1 generates an interrupt.
1 Enable greater than 4G I/O address interrupt generation
0 Disable greater than 4G I/O address interrupt generation
Reserved
18
Figure 17-26. PCI Express Error Disable Register (PEX_ERR_DISR)
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Table 17-25. PCI Express Error Disable Register Field Descriptions
Multiple errors disable. When set disables the setting of PEX_ERR_DR[ME] bit.
1 Disable multiple errors detection
0 Enable multiple errors detection
Reserved
PCI Express completion time-out disable. When set disables the setting of PEX_ERR_DR[PCT] bit.
1 Disable PCI Express completion time-out detection
0 Enable PCI Express completion time-out detection
Reserved
PCI Express CA completion disable. When set disables the setting of PEX_ERR_DR[PCAC] bit.
1 Disable completion with CA status detection
0 Enable completion with CA status detection
19
20
—
21
22
23
7
Figure
PCTD
All zeros
All zeros
24
8
17-26, controls the setting of the PCI Express error
Description
Description
—
9
PCACD PNMD CDNSCD CRSNCD ICCAD IACAD
10
11
—
12
Freescale Semiconductor
13
Access: Read/Write
14
15
31