MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 485

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 10-20
10.5.4.6
The MCR, shown in
software to reset the SEC.
Offset 0x3_1030
Freescale Semiconductor
Reset
Reset
22-23
24-29
0–21
Bits
W
W
16-23
24-31
32-39
40-47
48-55
56-63
R
R
0–15
Bits
32
CHN3_EU_PR_CNT
0
describes the fields of the IP block revision register.
Master Control Register (MCR)
Priority
Name
IP_CFG
IP_MN
IP_INT
IP_MJ
—
—
Name
IP_ID
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
—
—
Figure
39 40
CHN4_EU_PR_CNT
Table 10-21
10-20, controls certain functions in the controller and provides a means for
Reserved
Priority on Master Bus. The setting of these bits determines the transaction priority level
the SEC asserts to the SoC’s internal arbiter. The SEC does not dynamically alter its
priority level based on system congestion or SEC utilization; however, software may
change the SEC priority level in real time.
00 Lowest Priority (default)
01 Next Lowest Priority
10 Next Highest Priority
11 Highest Priority
Reserved
Table 10-20. IP Block Revision Register Fields
Table 10-21. Master Control Register Fields
IP block identifier. This field value is currently set as 0x0030
IP major revision number. This field value is currently set as 0x03.
IP minor revision number. This field value is currently set as 0x00
Reserved
IP block integration options. Field value depends on the options of the specific SoC
Reserved
IP block configuration options. Field value depends on the options of the specific SoC
Figure 10-20. Master Control Register
—
describes the MCR fields.
47
48
All zeros
All zeros
CHN3_BUS_PR_CNT
Description
Description
21
PRIORITY
22
23
55
24
56
Security Engine (SEC) 3.0
CHN4_BUS_PR_CNT
Access: Read/Write
—
29
GIH SWR
30
10-55
31
63