MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 555

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.5.7
The KEUIMR controls the setting of bits in the KEU interrupt status register (KEUISR), as described in
Section 10.7.5.6, “KEU Interrupt Status Register
corresponding KEUISR bit is always zero.
Masking an error bit allows for a hardware error condition to go potentially undetected. Therefore, extreme
care should be taken when masking errors, as invalid results may be produced. It is recommended that
errors only be masked during debug operation. This register may be reset by resetting the KEU.
The KEUIMR fields are shown in
Freescale Semiconductor
Reset
Field
Addr
R/W
Bits
58
59
60
61
62
63
0
KEU Interrupt Mask Register (KEUIMR)
Table 10-56. KEU Interrupt Status Register Signals Description (continued)
Name
—
OFE
OFU
0
IFO
IFE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
48
Output FIFO error. The KEU output FIFO was non-empty upon write of the KEU data size
register.
0 No error detected
1 Output FIFO non-empty error
Input FIFO error. The KEU input FIFO was non-empty upon generation of the done
interrupt.
0 No error detected
1 Input FIFO non-empty error
Reserved
Input FIFO overflow. The KEU input FIFO has been pushed while full.
0 No error detected
1 Input FIFO has overflowed
Output FIFO underflow. The KEU output FIFO was read while empty.
0 No error detected
1 Output FIFO has underflow error
Reserved
ICE
49
0
Figure 10-70. KEU Interrupt Mask Register
Figure
—
50
0
51
IE
1
10-70. The fields are defined in
ERE CE KSE DSE DE
52
(KEUISR)”. If a KEUIMR bit is set, then the
KEU 0x3_E038
53
R/W
54
Description
55
56
AE OFE IFE
57
0
Table
58
59
10-57.
—
60
Security Engine (SEC) 3.0
IFO OFU
61
62
—
63
10-125