MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 497

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10.7.1.9
The ICV size register, shown in
the number of most significant bytes in the received MAC tag supplied in context registers 3–4. AES
truncates the computed MAC in context registers 1–2 to the same number of bytes, and writes zeros in the
remaining LSB’s. It follows that the received MAC can be padded to 16 bytes with arbitrary data (not
necessarily zeros) when written into context registers 3–4. Acceptable values for ICV size are 8, 10, 12,
14 and 16 bytes in CMAC, or 8, 12, and 16 bytes in GCM. All other sizes are interpreted as 16.
In XCBC-MAC cipher mode, the ICV size register is not used. The received MAC (written to context
registers 9-10) is always truncated to the most significant 12 bytes, as defined in the XCBC-MAC-96 for
IPsec specification. The computed MAC written at the end of processing to Context Registers 1-2 is a full
16-byte MAC.
In CCM mode with ICV, the ICV size register is not used. Instead, the tag size is encoded within one of
the CCM formatting flags.
Freescale Semiconductor
Offset 0x3_4040
Reset
W
R
Bits
57
58
59
60
61
62
63
0
AESU ICV Size Register
Table 10-28. AESU Interrupt Mask Register Field Descriptions (continued)
Name
OFU
OFE
IFO
IFE
AE
—
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Address Error. An illegal read or write address was detected within the AESU address
space.
1 Address error disabled
0 Address error enabled
Output FIFO Error. Indicates the AESU Output FIFO was detected non-empty upon write
of AESU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO Error. Indicates he AESU Input FIFO was detected non-empty upon generation
of done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO Overflow. Indicates the AESU Input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
Output FIFO Underflow. Indicates the AESU output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Figure
Figure 10-28. AESU ICV Size Register
10-28, is used in AES hashing modes CMAC and GCM to specify
—
All zeros
Description
Security Engine (SEC) 3.0
56 57
Access: Read/Write
ICV Size
10-67
63