MPC8536DS Freescale Semiconductor, MPC8536DS Datasheet - Page 1249

• Manufacturer Part Number: MPC8536DS
• Description: BOARD DEV SYSTEM MPC8536E
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8536DS

• Contents: Board, Software and Documentation
• Processor Series: MPC85xx
• Core: e500
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 667 MHz
• Operating Supply Voltage: - 0.3 V to + 1.21 V
• Maximum Operating Temperature: + 105 C
• Data Ram Size: 32 KB
• Interface Type: SPI, USB
• Program Memory Type: DDR2, DDR3, SDRAM
• Core Size: 32 Bit
• Program Memory Size: 544KB
• Cpu Speed: 1.5GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 783
• Supply Voltage Range: 0.95V To 1.05V
• Rohs Compliant: Yes
• For Use With/related Products: MPC8536
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 19-15
19.3.3.4
SNotification, shown in
have sent the host a set device bits FIS with the notification bit. When the host receives a set device bits
FIS with the notification bit set to 1, the host should set the bit in SNotification corresponding to the value
of the PM port field in the received FIS. For example, if the PM port field is set to 7 then the host should
clear bit 7 by writing a 1 to it. Next, the host should generate an interrupt if the I bit of the set device bits
FIS is set to 1 and interrupts are enabled.
In this register, bits previously set are explicitly cleared by a write operation or by a power-on-reset
operation. If the register is not cleared due to a COMRESET, the software is responsible for clearing the
register as appropriate.
Freescale Semiconductor
31–16
15–12 SPM Select power management. Used to select a power management state. A non-zero value written
11–8
7–4
3–0
Bit
describes the SControl fields.
Name
SATA Interface Notification Register (SNotification)
SPD Speed. Highest allowed communication speed the interface is allowed to negotiate when
DET
IPM
—
MPC8536E PowerQUICC III Integrated Processor Reference Manual, Rev. 1
Reserved, should be cleared.
to this field will cause the power management state specified to be initiated. A value written to
this field is treated as a one-shot.
0000 No power management state transition requested
0001 Transition to the partial power management state initiated
0010 Transition to the slumber power management state initiated
0100 Transition to the active power management state initiated
All other values reserved
Interface power management. The enabled interface power management states can be invoked
via the SATA interface power management capabilities.
0000 No interface power management state restrictions
0001 Transitions to the partial power management state disabled
0010 Transitions to the slumber power management state disabled
0011 Transitions to both the partial and slumber power management states disabled
All other values reserved
interface communication speed is established.
0000 No speed negotiation restrictions
0001 Limit speed negotiation to a rate not greater than first-generation communication rate
0010 Limit speed negotiation to a rate not greater than second-generation communication rate
All other values reserved
Detection. Controls the host adapter device detection and interface initialization.
0000 No device detection or initialization action requested
0001 Perform interface communication initialization sequence to establish communication. This
0100 Disable the SATA interface and put PHY in offline mode
All other values reserved
Figure
is functionally equivalent to a hard reset and results in the interface being reset and
communications re-initialized. Upon a write to the SControl register that sets the DET field
to 0001, the host interface should transition to the HP1: HR_Reset [Delete space after
state and should remain in that state until the DET field is set to a value other than 0001
by a subsequent write to the SControl register.
19-16, is a 32-bit, write-one-to-clear register that conveys the devices that
Table 19-15. SControl Field Descriptions
Description
SATA Controller
19-19